Webinar: Removing the Risk from RISC-V using the RISC-V Trace Standard

Webinar: Removing the Risk from RISC-V using the RISC-V Trace Standard
by Admin on 12-30-2022 at 11:51 am

With the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support ecosystem is growing, with standards now defined for support technologies such as processor trace, which gives developers access to critical insights and

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Webinar: Implementing DFT in 2.5/3D designs using Tessent Multi-die software

Webinar: Implementing DFT in 2.5/3D designs using Tessent Multi-die software
by Admin on 12-30-2022 at 11:47 am

Next-generation devices increasingly feature complex architectures that connect dies vertically (3D IC) or side-by-side (2.5D) so they behave as a single device. The new Tessent Multi-die software delivers comprehensive automation for the highly complex DFT tasks associated with these 2.5D and 3D IC designs.

Tessent Multi-die

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DFT Moves up to 2.5D and 3D IC

DFT Moves up to 2.5D and 3D IC
by Daniel Payne on 10-06-2022 at 10:00 am

2.5D and 3D chiplets min

The annual ITC event was held the last week of September, and I kept reading all of the news highlights from the EDA vendors, as the time spent on the tester can be a major cost and the value to catching defective chips from reaching production is so critical. Chiplets, 2.5D and 3D IC design have caught the attention of the test world, … Read More


Efficient Memory BIST Implementation

Efficient Memory BIST Implementation
by Daniel Payne on 05-05-2022 at 10:00 am

Figure 1 min

Test experts use the acronym BIST for Built In Self Test, it’s the test logic added to an IP block that speeds up the task of testing by creating stimulus and then looking at the output results. Memory IP is a popular category for SoC designers, as modern chips include multiple memory blocks for fast, local data and register storage… Read More


Balancing Test Requirements with SOC Security

Balancing Test Requirements with SOC Security
by Tom Simon on 03-17-2022 at 6:00 am

Secure Test for SOCs

Typically, there is an existential rift between the on-chip access requirements for test and the need for security in SoCs. Using traditional deterministic scan techniques has meant opening up full read and write access to the flops in a design through the scan chains. Having this kind of access easily defeats the best designed… Read More


Tessent Streaming Scan Network Brings Hierarchical Scan Test into the Modern Age

Tessent Streaming Scan Network Brings Hierarchical Scan Test into the Modern Age
by Tom Simon on 11-15-2021 at 10:00 am

Streaming Scan Network

Remember when you had to use dial up internet or parallel printer cables connected directly to the printer to print something? Well even if you don’t remember these things, you know that now there is a better way. Regrettably, the prevalent methods used for hierarchical Design for Test (DFT) still look at lot like this – SoC level … Read More


Embedded Analytics Becoming Essential

Embedded Analytics Becoming Essential
by Tom Simon on 04-22-2021 at 6:00 am

Embedded Analytics

SoC integration offers huge benefits through reduced chip count in finished systems, higher performance, improved reliability, etc. A single die can contain billions of transistors, with multiple processors and countless subsystems all working together. The result of this has been rapid growth of semiconductor content … Read More


Observation Scan Solves ISO 26262 In-System Test Issues

Observation Scan Solves ISO 26262 In-System Test Issues
by Tom Simon on 03-23-2021 at 10:00 am

Observation scan for ISO 26262

Automotive electronic content has been growing at an accelerating pace, along with a shift from infotainment toward mission critical functions such as traction control, safety systems, engine control, autonomous driving, etc. The ISO 26262 automotive electronics safety standard evolved to help ensure that these systems… Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More


Getting Physical to Improve Test – White Paper

Getting Physical to Improve Test – White Paper
by Tom Simon on 08-26-2020 at 6:00 am

Calculating Total Critical Area

One of the most significant and oft repeated trends in EDA is the use of information from layout to help drive other parts of the design flow. This has happened with simulation and synthesis among other things. Of course, we think of test as a physical operation, but test pattern generation and sorting have been netlist based operations.… Read More