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Tessent Streaming Scan Network Brings Hierarchical Scan Test into the Modern Age

Tessent Streaming Scan Network Brings Hierarchical Scan Test into the Modern Age
by Tom Simon on 11-15-2021 at 10:00 am

Remember when you had to use dial up internet or parallel printer cables connected directly to the printer to print something? Well even if you don’t remember these things, you know that now there is a better way. Regrettably, the prevalent methods used for hierarchical Design for Test (DFT) still look at lot like this – SoC level DFT has not kept up with design scaling. Fortunately, Siemens EDA has developed an entirely new methodology for connecting core level scan to the top level. Let’s acknowledge that hierarchical scan was a huge step forward. But, accessing the cores has always been done with methods that look like a room full of telephone operators individually connecting calls.

Siemens has published an article titled “Tessent Streaming Scan Network: A no-compromise approach to DFT” that clearly lays out the problems endemic with implementing full chip test using core level scan and pin-mux connections. The paper describes the Streaming Scan Network (SSN) approach that they have developed to address these problems. Using the old pin-mux technique, chip designers have to plan up front how to efficiently use a limited number of chip-level pins to facilitate testing. Critical decisions have to be made early in the design phase and are difficult to change later in development. Even running identical blocks in parallel runs into limitations. Up front decisions have to be made about which sets of identical blocks can be run in parallel. Pipelining to each block must match, and the results need to come back serially, etc. Even here there is no free lunch. For most other types of blocks it is equally messy.

To highlight the limitations of the pin-mux approach, the Siemens paper discusses several other problems. Hardwired buses need to be the proper width and have to be routed in advance in anticipation of how patterns will be run later. Branches that have blocks with shorter scan chains will leave bandwidth wasted. The routing itself can be problematic, especially when block to block connections in the chip are only are made with abutment.

Streaming Scan Network
Streaming Scan Network used in a 6 core design

Tessent SSN solves the problems with the pin-mux scan approach, while at the same time adding flexibility and making test operations measurably more efficient. Each core is fitted with a Streaming Scan Host (SSH) which acts as a local intelligent controller. Each SSH has two external connections – an IJTAG 1687 interface for coordinating test activities and the parallel SSN data bus. The SSN bus, while parallel, is independent of the number or size of the scanned cores. Scan data is sent in packets. The scan data for each target block is completely abstracted from the SSN packets, which can be intermixed and carry scan data of any width. The result is that the SSN can operate at full capacity and unwrap the scan data where it is used to interface with the core’s internal scan chain.

Parallel testing of identical blocks is made easy with scan packet delivery in parallel, regardless of the location on the SSN. Tests can be run in parallel, and local results checking can flip a pass/fail bit for each instance. The bus can also help adjust for slower internal shift frequencies by sending faster packets that are narrower to keep in sync with these blocks. Having a packetized smart network for moving scan and test data anywhere on the chip means that test strategies can adapt to the specifics of the design, even after tapeout.

The article offers a lot more detail on the specifics and advantages of Siemens Streaming Scan Network. It certainly moves DFT from the age of modems and parallel printer cables into the modern age of broadband and networked printers. The full article is available on the Siemens website along with full product information on Streaming Scan Network.

Also Read:

Minimizing MCU Supply Chain Grief

Back to Basics in RTL Design Quality

APR Tool Gets a Speed Boost and Uses Less RAM

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