Bringing Hierarchy to DFT

Bringing Hierarchy to DFT
by Tom Simon on 01-30-2020 at 6:00 am

Tessent Hierarchical Flow

Hierarchy is nearly universally used in the SoC design process to help manage complexity. Dealing with flat logical or physical designs proved unworkable decades ago. However, there were a few places in the flow where flat tools continued to be used. Mentor lead the pack in the years around 1999 in helping the industry move from … Read More


ITC shines light on new Mentor Test announcements

ITC shines light on new Mentor Test announcements
by Tom Simon on 11-18-2019 at 10:00 am

The 50th International Test Conference was just held in Washington DC, where papers, sessions, workshops and announcements addressing the increasing complexity and expanding use of semiconductors showed that innovations in test are crucial to design and product success. Test methodologies and even the scope of test have … Read More


Automotive Market Pushing Test Tool Capabilities

Automotive Market Pushing Test Tool Capabilities
by Tom Simon on 07-09-2019 at 8:00 am

It’s easy to imagine that the main impetus for automotive electronics safety standards like ISO 26262 is the emergence of autonomous driving technology. However, even cars that do not offer this capability rely heavily on electronics for many critical systems. These include engine control, braking, crash sensors, and stability… Read More


Mentor’s Busy ITC and Major Test Product Updates

Mentor’s Busy ITC and Major Test Product Updates
by Tom Simon on 10-31-2018 at 1:00 pm

In conjunction with the 2018 International Test Conference, Mentor has several interesting test announcements. They also have a busy round of technical activities, including a number of technical papers, presentations, tutorials and a poster from a major customer about using Mentor. I’d like to touch on the two product related… Read More


Time is Money, Especially when Testing ICs

Time is Money, Especially when Testing ICs
by Daniel Payne on 05-24-2017 at 12:00 pm

Semiconductor companies are looking for ways to keep their business profitable by managing expenses on both the design and test side of electronic products, which is quite the challenge as the trends show increases in test pattern count and therefore test costs. Scan compression is a well-known technique first created over 15… Read More


Virtual Modeling Drives Auto Systems TTM

Virtual Modeling Drives Auto Systems TTM
by Bernard Murphy on 03-27-2017 at 7:00 am

The electronics market for automotive applications is distinguished by multiple factors. This is a very fast growing market – electronics now account for 40% of a car’s cost, up from 20% just 10 years ago. New technologies are gaining acceptance, for greener and safer operation and for a more satisfying consumer experience. Platforms… Read More


Mentor DefectSim Seen as Breakthrough for AMS Test

Mentor DefectSim Seen as Breakthrough for AMS Test
by Mitch Heins on 11-21-2016 at 4:00 pm

For decades, digital test has been fully automated including methodologies and automation for test pattern generation, grading and test time compression. Automation for analog and mixed-signal (AMS) IC test has not however kept pace. This is troubling as according to IBSapproximately 85% of SoC design starts are now AMS designs.… Read More


Cadence Adds New Dimension to SoC Test Solution

Cadence Adds New Dimension to SoC Test Solution
by Pawan Fangaria on 02-04-2016 at 7:00 am

It requires lateral thinking in bringing new innovation into conventional solutions to age-old hard problems. While the core logic design has evolved adding multiple functionalities onto a chip, now called SoC, the structural composition of DFT (Design for Testability) has remained more or less same based on XOR-based compression… Read More


Auto Introspection

Auto Introspection
by Bernard Murphy on 12-20-2015 at 4:00 pm

It is an indictment of our irrationality that our cars are now more health-conscious than we are. Increasingly safety-conscious readings of the ISO26262 standard now encourage that safety-critical electronics (anti-lock braking control for example) automatically self-test, not just at power-on but repeatedly as the car… Read More


Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location
by Beth Martin on 08-02-2015 at 7:00 am

Design sizes and complexities have grown exponentially (it’s a Law!), and consequentially the task of silicon test has become proportionally more expensive. The cost of testing a device is proportional to the amount of test data that is applied, and therefore the time it takes, which in turn is proportional to both design size … Read More