Automotive Market Pushing Test Tool Capabilities

Automotive Market Pushing Test Tool Capabilities
by Tom Simon on 07-09-2019 at 8:00 am

It’s easy to imagine that the main impetus for automotive electronics safety standards like ISO 26262 is the emergence of autonomous driving technology. However, even cars that do not offer this capability rely heavily on electronics for many critical systems. These include engine control, braking, crash sensors, and stability… Read More


Hierarchical RTL Based ATPG for an ARM A75 Based SOC

Hierarchical RTL Based ATPG for an ARM A75 Based SOC
by Tom Simon on 03-27-2019 at 5:00 am

Two central concepts have led to the growth of our ability to manage and implement larger and larger designs: hierarchy and higher levels of abstraction. Without these two approaches the enormous designs we are seeing in SOCs would not be possible. Hierarchy in particular allows the reuse of component blocks, such as CPU cores.… Read More


How to be Smart About DFT for AI Chips

How to be Smart About DFT for AI Chips
by Tom Simon on 01-31-2019 at 12:00 pm

We have entered the age of AI specific processors, where specialized silicon is being produced to tackle the compute needs of AI. Whether they use GPUs, embedded programmable logic or specialized CPUs, many AI chips are based on parallel processing. This makes sense because of the parallel nature of AI computing. As a result, in… Read More


The Pain of Test Pattern Bring-up for First Silicon Debug

The Pain of Test Pattern Bring-up for First Silicon Debug
by Daniel Payne on 08-22-2018 at 7:00 am

In the semiconductor world we have divided our engineering talent up into many adjacent disciplines and each comes with their own job titles: Design engineers, Verification engineers, DFT engineers, Test engineers. When first silicon becomes available then everyone on the team, and especially management all have a few big … Read More


Test Compression for Mission Critical SoCs

Test Compression for Mission Critical SoCs
by Mitch Heins on 12-20-2017 at 12:00 pm

With the advent of the Internet-of-Things (IoT), Industry 4.0, Cognitive Computing, and autonomous vehicles and robots we are seeing an unprecedented number of systems-on-a-chip (SoCs) going into mission-critical applications. To accomplish the complexity of these applications, SoCs are being manufactured in leading-edge… Read More


Automotive IC Design Requires a Unique EDA Tool Emphasis

Automotive IC Design Requires a Unique EDA Tool Emphasis
by Tom Dillinger on 08-14-2017 at 12:00 pm

Semiwiki readers are no doubt very familiar with the increasing impact of the automotive market on the semiconductor industry. The magnitude and complexity of the electronic systems that will be integrated into upcoming vehicle designs reflects the driver automation, safety, and entertainment features that are in growing… Read More


Finding Transistor-level Defects Inside of Standard Cells

Finding Transistor-level Defects Inside of Standard Cells
by Daniel Payne on 01-31-2017 at 12:00 pm

In the earliest days of IC design the engineering work was always done at the transistor-level, and then over time the abstraction level moved upward to gate-level, cell-level, RTL level, IP reuse, and high-level modeling abstractions. The higher levels of abstraction have allowed systems to be integrated into an SoC that can… Read More


Reducing the Cost of SoC Testing

Reducing the Cost of SoC Testing
by Daniel Payne on 12-16-2016 at 12:00 pm

Every year certain technology themes appear, like at ITC this year a big theme was how to reduce the cost of SoC testing. I spoke with Rob Knoth of Cadence by phone to hear more about this cost of test theme. Rob gave me an example of an SoC that takes 27 seconds on a tester, so at $0.04 per second in test costs amounts to $1.08 per part. If you… Read More


EDA Tool for ATPG – Refactor or Rewrite?

EDA Tool for ATPG – Refactor or Rewrite?
by Daniel Payne on 07-12-2016 at 3:00 pm

In the life of all EDA software tools comes that moment when new requirements make developers stop and ask, should I continue to refactor the existing code or just start all over from scratch using a new approach? Synopsys came to that junction point when ATPG run times were reaching days or even weeks on the largest IC designs, something… Read More


Cadence Adds New Dimension to SoC Test Solution

Cadence Adds New Dimension to SoC Test Solution
by Pawan Fangaria on 02-04-2016 at 7:00 am

It requires lateral thinking in bringing new innovation into conventional solutions to age-old hard problems. While the core logic design has evolved adding multiple functionalities onto a chip, now called SoC, the structural composition of DFT (Design for Testability) has remained more or less same based on XOR-based compression… Read More