Design of Power Electronics and Motor Drive Systems with PSIM

Design of Power Electronics and Motor Drive Systems with PSIM
by Admin on 09-01-2022 at 12:00 am

Free Webinar Series | April – October 2022

For many companies, the journey to product electrification and sustainable e-mobility solutions require completely transforming well-established design practices, acquiring non-core domain expertise, and integrating new design software within incumbent tech stacks.

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Arm and Cadence: Achieving Best Silicon Power, Performance, and Area

Arm and Cadence: Achieving Best Silicon Power, Performance, and Area
by Admin on 05-11-2022 at 12:00 am

Join Cadence and Arm to learn how you can achieve the best power, performance, area (PPA) and time to tapeout for Arm® CPU implementation using the latest Cadence® Digital Full Flow. This event covers topics including high-performance design for the Arm Cortex®-A710 and other Arm processors, energy-efficient CPU implementation

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Path Based UPF Strategies Explained

Path Based UPF Strategies Explained
by Tom Simon on 03-29-2022 at 6:00 am

Path Based UPF Semantics

The development of the Unified Power Format (UPF) was spurred on by the need for explicit ways to enable specification and verification of power management aspects of SoC designs. The origins of UPF date back to its first release in 2007. Prior to that several vendors had their own methods of specifying power management aspects … Read More


3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hiearchical Analysis

3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hiearchical Analysis
by Admin on 03-23-2022 at 12:00 am

Overview

A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs).  Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis also is extremely… Read More


Introduction to the Joules RTL Power Solution

Introduction to the Joules RTL Power Solution
by Admin on 03-08-2022 at 12:00 am

08 Mar 2022

Online

Event Details

Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow?

Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar.

Built on a multi-threaded frame-based architecture, the Cadence

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MBIST Power Creates Lurking Danger for SOCs

MBIST Power Creates Lurking Danger for SOCs
by Tom Simon on 01-25-2022 at 10:00 am

MBIST power emulation

The old phrase that the cure is worse than the disease is apropos when discussing MBIST for large SOCs where running many MBIST tests in parallel can exceed power distribution network (PDN) capabilities. Memory Built-In Self-Test (MBIST) usually runs automatically during power on events. Due to the desire to speed up test and … Read More


Physically Aware SoC Assembly

Physically Aware SoC Assembly
by Bernard Murphy on 10-26-2021 at 6:00 am

SoC Assembly min 1

We used to be comfortable with the idea that the worlds of logical design and physical implementation could be largely separated. Toss the logical design over the wall, and the synthesis and P&R teams would take care of the rest. That idea took a bit of a hit when we realized that synthesis had to become physically aware. The synthesis… Read More


Cerebrus, the ML-based Intelligent Chip Explorer from Cadence

Cerebrus, the ML-based Intelligent Chip Explorer from Cadence
by Kalar Rajendiran on 07-29-2021 at 10:00 am

Screen Shot 2021 07 21 at 4.39.06 PM

Electronic design automation (EDA) has come a long way from its beginnings. It has enabled chip engineers from specifying designs directly in layout format during the early days to today’s capture in RTL format. Every advance in EDA has made the task of designing a chip easier and increased the design team productivity, enabling… Read More


Netlist CDC. Why You Need it and How You do it.

Netlist CDC. Why You Need it and How You do it.
by Bernard Murphy on 08-25-2020 at 6:00 am

netlist cdc min

The most obvious question here is “why do I need netlist CDC?” A lot of what you’re looking for in CDC analysis is really complex behaviors, like handshakes between different clock domains, correct gray coding in synchronizing FIFOs, eliminating quasi-static signals and the like. Deeply functional, system-level intent stuff.… Read More


AI Interposer Power Modeling and HBM Power Noise Prediction Studies

AI Interposer Power Modeling and HBM Power Noise Prediction Studies
by Mike Gianfagna on 02-07-2020 at 6:00 am

Picture1

I attended a session on 2.5D silicon interposer analysis at DesignCon 2020. Like many presentations at this show, ecosystem collaboration was a focus. In this session, Jinsong Hu (principal application engineer at Cadence) and Yongsong He (senior staff engineer at Enflame Tech) presented approaches for interposer power modeling… Read More