Synopsys Virtual Prototyping Day 2024

Synopsys Virtual Prototyping Day 2024
by Admin on 07-03-2024 at 3:23 pm

Join us at Virtual Prototyping Day 2024 to hear about the latest deployed virtual prototyping innovations. This event highlights applications from around the world using the latest virtual prototyping technology, covering applications from automotive, AI, and data center domains.​

​Industry leaders will share their experiences… Read More


LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis

LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis
by Daniel Nenni on 07-03-2024 at 2:00 pm

The Role of Realistic Workloads and Massively Parallel Power Analysis

As the complexity of modern System-on-Chip (SoC) designs continues to rise, achieving energy efficiency measured as performance per watt has become a crucial design goal. With the increasing demand for powerful, multifunctional chips, balancing performance with power consumption has become essential. Realistic workloads… Read More


CircuitSutra Technologies at the 2024 Design Automation Conference

CircuitSutra Technologies at the 2024 Design Automation Conference
by Daniel Nenni on 06-17-2024 at 4:00 pm

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The Design Automation Conference (DAC) is a premier event that focuses on the design and automation of electronic systems. It is an annual conference that has been held since 1964, making it one of the longest-running and most established events in the field of electronic design automation (EDA).

DAC offers outstanding training,… Read More


CEO Interview: Dieter Therssen of Sigasi

CEO Interview: Dieter Therssen of Sigasi
by Daniel Nenni on 06-07-2024 at 6:00 am

Dieter Therssen

Dieter Therssen obtained his master’s degree in Electronics Engineering from KU Leuven in 1987. He started his career as a hardware design engineer, using IMEC’s visionary tools and design methodologies in the early days of silicon integration.

Since then, Dieter developed his career across many digital technologies,… Read More


Webinar: Maximize Productivity with Deep Insights into PPA Trajectories

Webinar: Maximize Productivity with Deep Insights into PPA Trajectories
by Admin on 05-30-2024 at 3:18 pm

The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to 

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Webinar: Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing

Webinar: Silicon.da: The First Integrated SLM Analytics Solution from Design Through Manufacturing
by Admin on 05-30-2024 at 3:15 pm

Today’s advanced node chip designs are faced with many new complexities which require more verification, more validation and more analysis. The resulting data from these added steps has also grown exponentially and engineers need a way to efficiently analyze this information. The result is a new paradigm shift which has led

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Synopsys Design IP for Modern SoCs and Multi-Die Systems

Synopsys Design IP for Modern SoCs and Multi-Die Systems
by Kalar Rajendiran on 04-11-2024 at 10:00 am

Synopsys IP Scale, a Sustainable Advantage

Semiconductor intellectual property (IP) plays a critical role in modern system-on-chip (SoC) designs. That’s not surprising given that modern SoCs are highly complex designs that leverage already proven building blocks such as processors, interfaces, foundational IP, on-chip bus fabrics, security IP, and others. This… Read More


Webinar: Automating the Integration Workflow with IP Centric Design

Webinar: Automating the Integration Workflow with IP Centric Design
by Admin on 04-08-2024 at 3:14 pm

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During a project, subsystem and full-chip integration plays a crucial role. Integration can be particularly challenging on large SoCs with distributed teams due to complexity of the integration process, multi-site infrastructure issues, as well as the need to collaborate … Read More


Webinar: Enabling SoC Security and Reliability for HPC, AI & IoT with NVM OTP IP in TSMC N5

Webinar: Enabling SoC Security and Reliability for HPC, AI & IoT with NVM OTP IP in TSMC N5
by Admin on 03-26-2024 at 2:23 pm

Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb of repair information to meet yield requirements. Designers are facing the challenges of creating secure,

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