Role of MIPI IP in New Automotive SoC Architectures

Role of MIPI IP in New Automotive SoC Architectures
by Admin on 10-20-2021 at 12:00 am

Wednesday, October 20, 2021 | 10:00 -11:00 a.m. PT

SoCs for Automotive applications such as ADAS, Infotainment, and connected vehicles are shifting to a more domain-based architecture. As a result, the car’s electronics for such applications are requiring a major redesign for a more efficient connectivity with the utmost reliability,

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De-risking RFICs and High Speed SoCs from Electromagnetic Crosstalk

De-risking RFICs and High Speed SoCs from Electromagnetic Crosstalk
by Admin on 09-13-2021 at 12:00 am

Time:
September 13, 2021
8 AM EDT / 1 PM BST / 5:30 PM IST

Venue:
Onlineo

About this Webinar

In today’s near threshold designs, trends like tighter integration and increasing layout density on advanced nodes, frequency escalation (5G) and complex packaging scenarios are making the need for accurate and efficient electromagnetic… Read More


Obtaining Early Analog Block Area Estimates

Obtaining Early Analog Block Area Estimates
by Tom Simon on 07-13-2021 at 6:00 am

Animate Preview Area Estimation

I’ve written before about Pulsic’s Animate Preview software, which is extremely helpful in completing placement in analog blocks so that they are ready for routing. Analog design automation has always been a tough proposition, but Animate Preview looks like a promising tool, with practical benefits. Obtaining DRC clean placement… Read More


Analog Sensing Now Essential for Boosting SOC Performance

Analog Sensing Now Essential for Boosting SOC Performance
by Tom Simon on 06-03-2021 at 6:00 am

analog sensing

In today’s System-on-Chip (SOC), analog blocks are used in many places such as I/O cells for communication, PLLs for generating clocks, LDO’s for converting supply voltage to internal rail voltage, Sensors for qualifying external characteristics such as temperature, light, motion, etc. However new advanced designs now require… Read More


Webinar: Challenges in creating large High Performance Compute SoCs in advanced geometries

Webinar: Challenges in creating large High Performance Compute SoCs in advanced geometries
by Daniel Nenni on 05-17-2021 at 6:00 am

Sondrel Webinar 1

When we think about Compute and AI SoCs, we often focus on the huge numbers of calculations being carried out every second, and the ingenious IPs that are able to reach such high levels of performance. However, there also exists a significant challenge in keeping the vast quantities of data flowing around the chip which is solved … Read More


Optimizing SoC performance in-life with Embedded Analytics

Optimizing SoC performance in-life with Embedded Analytics
by Admin on 05-12-2021 at 12:00 am

In many aspects of our lives, increasingly intelligent subsystems will do the thinking for us. 5G networks will self-tune to maximize their data throughput. Automation, with the help of AI, robotics, and the internet of things, is playing an increasing role in manufacturing. Vehicles are becoming ever more intelligent and autonomous.

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Circuit Simulator 2X/3X Faster than FastSPICE on Full Chip Simulation

Circuit Simulator 2X/3X Faster than FastSPICE on Full Chip Simulation
by Daniel Nenni on 11-11-2020 at 1:00 am

Typical applications for SPICE simulators include analog, small and middle size digital and memory blocks, whereas FastSPICE simulators targets larger blocks or full chip simulations including memory circuits, SoCs. SPICE is very accurate but cannot handle large designs and simulation time can be extensive. While FastSPICE… Read More


Digital Design Technology Symposium!

Digital Design Technology Symposium!
by Daniel Nenni on 10-07-2020 at 6:00 am

Synopsys Digital Design Symposium 2020
Virtual events are coming fast and furious. Even though we are sheltering there is still the need to pick and choose carefully because time really is big money inside the semiconductor design ecosystem, absolutely.

Synopsys virtual events are high on my list for three reasons:

  1. They are very well organized and professionally done
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WEBINAR: Design Adaptive eFPGA IP

WEBINAR: Design Adaptive eFPGA IP
by Daniel Nenni on 09-18-2020 at 10:00 am

Menta Adaptive Design eFPGA Webinar 1

Since the start of PROMS, PLDs and FPGAs we have learned the importance of programmability in modern semiconductor design. Today we have eFPGAs for “design adaptive” embedded programmability and that is what this webinar is all about.

Several key points are discussed starting with the Law of Accelerating Returns as it applies… Read More


Can you really meet your SoC design schedule without a good GUI?

Can you really meet your SoC design schedule without a good GUI?
by Daniel Nenni on 08-31-2020 at 10:00 am

flow3 1

Talk to the members of a digital design team and you will always find two types of users. One who likes using the GUI while working on his design and the other who is passionate about using scripts and the command line options. This is akin to the two camps of users who either love either good old Vi/Vim or the ever versatile Emacs editor.… Read More