Digital Design Technology Symposium!

Digital Design Technology Symposium!
by Daniel Nenni on 10-07-2020 at 6:00 am

Synopsys Digital Design Symposium 2020
Virtual events are coming fast and furious. Even though we are sheltering there is still the need to pick and choose carefully because time really is big money inside the semiconductor design ecosystem, absolutely.

Synopsys virtual events are high on my list for three reasons:

  1. They are very well organized and professionally done
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WEBINAR: Design Adaptive eFPGA IP

WEBINAR: Design Adaptive eFPGA IP
by Daniel Nenni on 09-18-2020 at 10:00 am

Menta Adaptive Design eFPGA Webinar 1

Since the start of PROMS, PLDs and FPGAs we have learned the importance of programmability in modern semiconductor design. Today we have eFPGAs for “design adaptive” embedded programmability and that is what this webinar is all about.

Several key points are discussed starting with the Law of Accelerating Returns as it applies… Read More


Can you really meet your SoC design schedule without a good GUI?

Can you really meet your SoC design schedule without a good GUI?
by Daniel Nenni on 08-31-2020 at 10:00 am

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Talk to the members of a digital design team and you will always find two types of users. One who likes using the GUI while working on his design and the other who is passionate about using scripts and the command line options. This is akin to the two camps of users who either love either good old Vi/Vim or the ever versatile Emacs editor.… Read More


High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
by admin on 08-04-2020 at 10:00 am

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential
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System-level Power and Performance Optimization of AI SoC Architectures

System-level Power and Performance Optimization of AI SoC Architectures
by Daniel Nenni on 07-22-2020 at 10:00 am

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The investment into tackling AI hardware acceleration has grown at breakneck speeds, with many vendors starting 2nd, 3rd, or 4th generation designs. Due to the fierce competition and ever-growing application opportunities for AI, machine learning algorithms, and compilers, architectures are evolving rapidly and branching… Read More


Introducing Ansys RaptorH: SoC, Mixed-Signal and RFIC Electromagnetic Modeling

Introducing Ansys RaptorH: SoC, Mixed-Signal and RFIC Electromagnetic Modeling
by Admin on 06-02-2020 at 8:30 pm

June 2, 2020

8:30 PM (EDT)

Venue:
Online

Ansys RaptorH adds to Ansys’ comprehensive set of electromagnetic (EM) field solver modeling capabilities, which extend from devices to chips to full electronics systems. The enhanced on-silicon EM simulation now includes the Ansys HFSS gold-standard engine integrated into an easy-to-use

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AI SoC Architectures for Smart, Efficient Edge Computing

AI SoC Architectures for Smart, Efficient Edge Computing
by admin on 04-30-2020 at 10:00 am

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The concept of edge computing—putting low power servers close to the application instead of relying solely on “the cloud”–may not be a novel idea, but for 5G and the Internet of Things, adding AI capabilities to edge computing will be revolutionary.  SoC designs will need to provide distributed intelligence in hardware
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Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards

Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards
by Admin on 03-17-2020 at 11:00 am

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Tue, Mar 17, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**
ABSTRACT
Presently, emulation and FPGA-based prototyping are essential verification and validation techniques for a SoC, ASIC designs and become irreplaceable in pre-silicon verification of Deep Learning Accelerator designs. Challenges of
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Who is Driving This Car Anyway?

Who is Driving This Car Anyway?
by Roger C. Lanctot on 01-01-2020 at 10:00 am

Who is Driving This Car Anyway

My Lyft driver in San Jose thought his Hyundai had “autopilot,” alluding I suspected, to Tesla Motors’ feature of the same name which has placed that company at the forefront of driving automation development and the focal point of fatal crash investigations. Before either of us got hurt I gently disabused my driver of his dangerous… Read More


Free webinar – Accelerating data processing with FPGA fabrics and NoCs

Free webinar – Accelerating data processing with FPGA fabrics and NoCs
by Tom Simon on 10-14-2019 at 10:00 am

FPGAs have always been a great way to add performance to a system. They are capable of parallel processing and have the added bonus of reprogramability. Achronix has helped boost their utility by offering on-chip embedded FPGA fabric for integration into SoCs. This has had the effect of boosting data rates through these systems… Read More