Formal Verification of Registers and SoC Assembly in Collaboration with Jasper™ and OneSpin™

Formal Verification of Registers and SoC Assembly in Collaboration with Jasper™ and OneSpin™
by Admin on 04-28-2022 at 12:00 am

Description
Automatic generation of System Verilog Assertions for block level register specification, chip-level RTL design aggregating leaf level design, and RTL wrapper connectivity checks at SoC level.

Apr 28, 2022 10:00 AM in Pacific Time (US and Canada)

REGISTER HERE

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D&R IP SoC Silicon Valley 2022

D&R IP SoC Silicon Valley 2022
by Admin on 04-26-2022 at 12:00 am

When : April 26th 2022

Where : Computer History Museum
1401 N. Shoreline Blvd
Mountain View, CA 94043, USA

D&R IP-SoC Silicon Valley 2022 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.

IP-SoC providers, the seed of innovation in Electronic Industry,… Read More


Balancing Test Requirements with SOC Security

Balancing Test Requirements with SOC Security
by Tom Simon on 03-17-2022 at 6:00 am

Secure Test for SOCs

Typically, there is an existential rift between the on-chip access requirements for test and the need for security in SoCs. Using traditional deterministic scan techniques has meant opening up full read and write access to the flops in a design through the scan chains. Having this kind of access easily defeats the best designed… Read More


Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App

Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
by Daniel Nenni on 03-09-2022 at 10:00 am

Wednesday, March 9, 2022 | 10-10:45 a.m. PST

Complex bus protocols, increased on-chip functionalities, coupled with limited shared I/O resources, result in complex wiring connections in SoCs with numerous muxing schemes.

Simulation and structural analysis approaches require huge effort and may lead to bug escapes making

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Webinar: Beyond the Basics of IP-based Digital Design Management

Webinar: Beyond the Basics of IP-based Digital Design Management
by Daniel Payne on 03-08-2022 at 10:00 am

Digital Design Flow

According to the ESD Alliance, the single biggest revenue category in our industry is for semiconductor IP, so the concept of IP reuse is firmly established as a way to get complex products to market more quickly and reducing risk. On the flip side, with hundreds or even thousands of IP blocks in a complex SoC, how does a team, division… Read More


Power Analysis in Advanced SoCs. A Siemens EDA Perspective

Power Analysis in Advanced SoCs. A Siemens EDA Perspective
by Bernard Murphy on 02-23-2022 at 6:00 am

Power verification methods min

The success of modern battery-powered products depends as much on useful operating time between charges as on functionality. FinFET process technologies overtook earlier planar CMOS in part because they significantly reduce leakage power. But they exacerbate dynamic power consumption thanks to increased pin capacitances.… Read More


Exploring a Software First Approach to Avoid SoC Re-spins

Exploring a Software First Approach to Avoid SoC Re-spins
by Daniel Nenni on 02-09-2022 at 10:00 am

Traditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems.  To conquer the verification challenge of complex SoCs, companies are shifting their development paradigm to a software first approach.  By considering the target software

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From Now to 2025 – Changes in Store for Hardware-Assisted Verification

From Now to 2025 – Changes in Store for Hardware-Assisted Verification
by Daniel Nenni on 01-12-2022 at 6:00 am

Jean Marie Brunet

Lauro Rizzatti recently interviewed Jean-Marie Brunet, vice president of product management and product engineering in the Scalable Verification Solution division at Siemens EDA, about why hardware-assisted verification is a must have for today’s semiconductor designs. A condensed version of their discussion is below.… Read More


Cliosoft and Microsoft to Collaborate on the RAMP Program

Cliosoft and Microsoft to Collaborate on the RAMP Program
by Kalar Rajendiran on 01-06-2022 at 6:00 am

Cliosoft RAMP SemiWiki

We have all heard of many advanced technological inventions and products from the defense sector that subsequently got commercialized. While most of the Defense Advanced Research Projects Agency (DARPA) projects are classified secrets, many military innovations have had great influence in the commercial sector in the fields… Read More


High-Speed Data Converters Accelerating Automotive and 5G Products

High-Speed Data Converters Accelerating Automotive and 5G Products
by Kalar Rajendiran on 11-10-2021 at 10:00 am

Enabling Technology Omni Design SWIFT

While the trend towards System-on-Chip (SoC) has been gathering momentum for quite some time, the primary driver has been integration of digital components, spurred by Moore’s law. Integrating more and more digital circuitry into a single chip has been consistently beneficial for performance, power, form factor and economic… Read More