Semiconductor intellectual property (IP) plays a critical role in modern system-on-chip (SoC) designs. That’s not surprising given that modern SoCs are highly complex designs that leverage already proven building blocks such as processors, interfaces, foundational IP, on-chip bus fabrics, security IP, and others. This… Read More
Tag: soc
Webinar: Automating the Integration Workflow with IP Centric Design
(Work email required for verified registration)
During a project, subsystem and full-chip integration plays a crucial role. Integration can be particularly challenging on large SoCs with distributed teams due to complexity of the integration process, multi-site infrastructure issues, as well as the need to collaborate … Read More
Webinar: Enabling SoC Security and Reliability for HPC, AI & IoT with NVM OTP IP in TSMC N5
Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb of repair information to meet yield requirements. Designers are facing the challenges of creating secure,
D&R IP-SoC Silicon Valley 2024 Day
A worldwide connected Event !!
D&R IP-SoC Silicon Valley 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.
IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and … Read More
Agile Analog Technology Showcase Event
Learn how innovative analog IP can help analog design engineers.
Agile Analog is transforming the analog IP industry, with Composa, our configurable, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion, Power Management, IC Monitoring,… Read More
Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly
Webinar: Automated Power Intent Management Pre-synthesis for Large SoC Designs
SUMMARY
With increasing chip design complexity, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases, UPF creation and assembly are among the key … Read More
Webinar: Auto-generation of Verification Infrastructure for IP to SoC
DVClub Europe Meeting –November 2023
Agenda (BST):
12.00 GMT – Welcome and Introduction
Mike Bartley,Tessolve
12.00 GMT – Saving Development Time by Automating Verification infra from specifications
Anupam Bakshi, Agnisys
12.30 GMT – Generation of Functional Coverage for RISC-V Processor Verification
Webinar: Automated Constraints Promotion Methodology from IP to SoC Designs for Complex Designs
IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints
ASIP University Day 2023
ASIP University Day: Domain-Specific Processor Design using ASIP Designer
Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements, and fixed