Agile Analog Technology Showcase Event

Agile Analog Technology Showcase Event
by Admin on 02-26-2024 at 8:09 pm

Learn how innovative analog IP can help analog design engineers.

Agile Analog is transforming the analog IP industry, with Composa, our configurable, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion, Power Management, IC Monitoring,… Read More


Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs

Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
by Admin on 01-08-2024 at 2:00 pm

Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly

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Webinar: Automated Power Intent Management Pre-synthesis for Large SoC Designs

Webinar: Automated Power Intent Management Pre-synthesis for Large SoC Designs
by Admin on 11-20-2023 at 3:08 pm

SUMMARY

With increasing chip design complexity, power intent management is becoming a requirement by chip designers. Power intent (UPF) databases are getting more and more complex and difficult to handle by designers without a reasonable level of automation. Query UPF databases, UPF creation and assembly are among the key … Read More


Webinar: Auto-generation of Verification Infrastructure for IP to SoC

Webinar: Auto-generation of Verification Infrastructure for IP to SoC
by Admin on 11-15-2023 at 3:44 pm

DVClub Europe Meeting –November 2023

Agenda (BST):

12.00 GMT – Welcome and Introduction

Mike Bartley,Tessolve

12.00 GMT – Saving Development Time by Automating Verification infra from specifications

Anupam Bakshi, Agnisys

12.30 GMT – Generation of Functional Coverage for RISC-V Processor Verification

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Webinar: Automated Constraints Promotion Methodology from IP to SoC Designs for Complex Designs

Webinar: Automated Constraints Promotion Methodology from IP to SoC Designs for Complex Designs
by Admin on 10-30-2023 at 2:49 pm

IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints

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CadenceCONNECT: Vietnam Technology Seminar 2023

CadenceCONNECT: Vietnam Technology Seminar 2023
by Admin on 10-04-2023 at 4:37 am

Overview

CadenceCONNECT Vietnam Technology Seminar 2023 will introduce you to optimized design methodologies for electronics system applications. The event brings together Cadence technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues and

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Webinar: UCIe-Based Chiplet Verification – from IP to SoC

Webinar: UCIe-Based Chiplet Verification – from IP to SoC
by Admin on 09-15-2023 at 12:15 pm

About

Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality… Read More