ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era
by Scotten Jones on 01-15-2021 at 6:00 am

Slide3

I was asked to give a talk at the 2021 ISS conference and the following is a write up of the talk.

The title of the talk is “Logic Leadership in the PPAC era”.

The talk is broken up into three main sections:

  1. Background information explaining PPAC and Standard Cells.
  2. A node-by-node comparisons of companies running leading edge logic
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2020 was a Mess for Intel

2020 was a Mess for Intel
by Robert Maire on 01-13-2021 at 10:00 am

Intel 2020 Mess

Understanding Intel’s future means understanding Intel’s past

Yes, there are two paths you can go by, but in the long run. There’s still time to change the road you’re on.

Intel is at a crossroad. The road they have been on since inception, and the road that has differentiated them from the rest of the pack… Read More


A Research Update on Carbon Nanotube Fabrication

A Research Update on Carbon Nanotube Fabrication
by Tom Dillinger on 12-22-2020 at 10:00 am

IV measurement testchip

It is quite amazing that silicon-based devices have been the foundation of our industry for over 60 years, as it was clear that the initial germanium-based devices would be difficult to integrate at a larger scale.  (GaAs devices have also developed a unique microelectronics market segment.)  More recently, it is also rather … Read More


Apple A14 Die Annotation and Analysis – Terrifying Implications For The Industry

Apple A14 Die Annotation and Analysis – Terrifying Implications For The Industry
by Dylan Patel on 12-20-2020 at 10:00 am

Apple A14 Die Analysis

SemiAnalysis and SkyJuice have teamed up in order to analyze the A14 die shot from ICmasters. Our previous analysis of the A14, delved into why Apple and TSMC have deviated from previous generations when comparing theoretical logic transistor density to a real world utilized transistor density.

Read More

SMIC Blacklist puts ASML in Jam

SMIC Blacklist puts ASML in Jam
by Robert Maire on 12-20-2020 at 6:00 am

SMIC Blacklisted US

US BIS confirms our prediction of “blacklisting” SMIC
SMIC embargoed from 10NM or better technology
Likely related to ASML pressure & WH scorched earth

Not just the stock

We had received a lot of feedback on our Nov 30th note regarding blacklisting of SMIC suggesting that we were wrong and the only thing blacklisted… Read More


Advanced Process Development is Much More than just Litho

Advanced Process Development is Much More than just Litho
by Tom Dillinger on 12-16-2020 at 10:00 am

Vt distribution

The vast majority of the attention given to the introduction of each new advanced process node focuses on lithographic updates.  The common metrics quoted are the transistors per mm**2 or the (high-density) SRAM bit cell area.  Alternatively, detailed decomposition analysis may be applied using transmission electron microscopy… Read More


Design Considerations for 3DICs

Design Considerations for 3DICs
by Tom Dillinger on 12-14-2020 at 6:00 am

LVS flow phases

The introduction of heterogeneous 3DIC packaging technology offers the opportunity for significant increases in circuit density and performance, with corresponding reductions in package footprint.  Yet, the implementation of a complex 3DIC product requires a considerable investment in methodology development for all… Read More


The Semiconductor Industry Has High Hopes That Biden Will Change Tracks

The Semiconductor Industry Has High Hopes That Biden Will Change Tracks
by Terry Daly on 12-13-2020 at 8:00 am

US China Semiconductor Biden

What is the “right track” for US-China trade relations?

The semiconductor industry has been squarely in the crosshairs of US-China trade tensions for four years. As the US faces a presidential leadership transition, will a Biden administration change the dynamic? The chip industry is counting on it, and China hopes so too.

In … Read More


Apple’s A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC’s Density Claims

Apple’s A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC’s Density Claims
by Dylan Patel on 12-11-2020 at 6:00 am

Apple 14 TSMC 5nm Transister Packing 1

Our friends over at ICmasters have delved into the package of the Apple A14 Bionic. The die size has been unmasked, and it stands in at 88mm2. Despite cramming in 11.8 billion transistors, the die size is incredibly small thanks to utilization of TSMC’s 5nm process node.

The march of progress is not all rosy. Apple’s chips have historically… Read More


IEDM 2020 Starts this Weekend

IEDM 2020 Starts this Weekend
by Scotten Jones on 12-10-2020 at 6:00 am

IEDM 2020 Logo

As I have discussed before, I believe that IEDM is the premier technical conference for understanding leading edge process technologies. Beginning this coming weekend, this year’s edition of IEDM will be held virtually, and I highly recommend attending.

The conference held a press briefing last Monday. The tutorial and short… Read More