Synopsys Low Power Workshop Offers Breadth and Depth

Synopsys Low Power Workshop Offers Breadth and Depth
by Bernard Murphy on 06-18-2019 at 5:00 am

Synopsys seems to particularly excel at these events, whether in half-day tutorials at conferences or, as in this case, in a full-day on-site workshop. You might think there’s not much that can be added in this domain, other than to bring low-power newbies up to speed, but you’d be wrong. This event set the stage with surveys on needs… Read More


Magillem offers a practical UPF power flow

Magillem offers a practical UPF power flow
by Tom Simon on 05-28-2019 at 10:00 am

We already know that IP-Xact is extremely useful for managing IP and SOC design specifications, yet it may come as a surprise to learn that it also can be used to form the basis of a power flow too. There are design tools that read UPF to help implement and verify designs, however it can be extremely useful to understand the interplay … Read More


Foundational Excellence in a Laid-Back Style

Foundational Excellence in a Laid-Back Style
by Bernard Murphy on 04-24-2019 at 7:00 am

I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL. When you hear a line like that, you assume a heavy dose of marketing spin, but here it really is fact. I don’t know of… Read More


CEO Interview: Cristian Amitroaie of AMIQ EDA

CEO Interview: Cristian Amitroaie of AMIQ EDA
by Bernard Murphy on 07-05-2018 at 7:00 am

AMIQ EDA has caught my attention over the last few months. My first impression was that this was just another small IDE company trying to compete with established and bundled IDEs from the big 3, a seemingly insurmountable barrier. This view was challenged by an impressive list of testimonials, not just from the little guys but also… Read More


Low Power Verification Shifting Left

Low Power Verification Shifting Left
by Bernard Murphy on 05-08-2018 at 11:00 pm

I normally think of shift left as a way to move functional verification earlier in design, to compress the overall design cycle. But it can also make sense in other contexts, one particularly important example being power intent verification.

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If you know anything about power intent, you know that it affects pretty… Read More


Getting Low Power Design Right in Mixed Signal Designs

Getting Low Power Design Right in Mixed Signal Designs
by Bernard Murphy on 05-12-2016 at 4:00 pm

Mixed-signal design creates all sorts of interesting problems for implementation and verification Image Removedflows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements… Read More


Body-biasing for ARM big or LITTLE in GF 22FDX

Body-biasing for ARM big or LITTLE in GF 22FDX
by Don Dingee on 05-04-2016 at 4:00 pm

GLOBALFOUNDRIES has been evangelizing their 22FDX FD-SOI process for a few months; readers may have seen Tom Simon’s write-up of their preview at ARM TechCon. Dr. Joerg Winkler recently gave an updated webinar presentation of their approach in an implementation of ARM Cortex-A17 core.

By now, you’ve probably heard that 22FDX… Read More


A Brief History of Defacto Technologies

A Brief History of Defacto Technologies
by Pawan Fangaria on 03-04-2016 at 7:00 am

In early 2000s, semiconductor design at RTL level was gaining momentum. The idea was to process more design steps such as insertion of test and other design structures upfront at the RTL level. The design optimization and verification were to be done at the RTL level to reduce long iterations through gate level design because changes… Read More


Something Old, Something New…EDA and Verification

Something Old, Something New…EDA and Verification
by Ellie Burns on 10-04-2015 at 12:00 pm

When I got the opportunity to blog about verification, I thought, what new and interesting things should I talk about? Having started my EDA career in 1983, I often feel like one of the “oldies” in this business…remember when a hard drive required a static strap, held a whopping 33 MB, and was the size of a brick? Perhaps they should … Read More