DACis just 33 days away and who wouldn’t want a cool GoPro camerato play with? Your manager will certainly want you to first check out what’s new at DAC if your job involves getting to RTL signoff on time and within budget. The creative folks at Atrenta have figured out how to attract us with the offer of winning a GoPro camera, however you at least have to attend a product session in their suites to get your name into the drawing, and there will be two winners per day, plus you don’t even have to be present to win (my favorite kind of contest).
In 2013 at the Atrenta booth and suites you heard a lot about IP signoff, and the news this year has morphed into SoC signoff. You’ll have 10 suite sessions to choose from at booth #1933, based upon your specialty, and each session has a simple registration process:
- IP Signoff – use a standardized set of design and verification checks on internal IP and 3rd party IP
- SoC Signoff – inspect and integrate IP to create an SoC for a billion or more gates
- SpyGlass Platform – get to RTL signoff using SpyGlass by analyzing the structure, function, CDC, timing, power, DFT and physical challenges
- BugScope – discover more corner case bugs using auto-generated assertions, functional coverage properties and verification metric apps
- SpyGlass Power – try a power management tool flow to estimate power, and optimize RTL
- SpyGlass Constraints – get timing constraints under control with SDC validation, management and verification
- SpyGlass CDC & Advanced Lint – reach CDC verification closure faster
- SpyGlass DFT, DSM, MBIST – improve product quality through higher coverage tests and built-in testability
- GenSys – use some automation to automate chip assembly
- SpyGlass Physical – analyze your RTL against physical rules prior to tape-out, while improving your floor plan
DAC has designer tracks each year, and Atrenta engineers are participating in five of these on Monday to Wednesday:
- A Comprehensive Metrics Driven Methodology to Measure and Improve Soft-IP Quality
- CDC Aware Power Reduction for Soft IPs
- SoC Connectivity Checks – Driving Design Intent Validation
- The Evil’s in the Edits
- Effective RTL Coding Rules to Avoid Simulation Shoot-Thru
An impressive thing to note about the designer tracks is how most of the speakers and authors are real engineers, not the marketing guys and gals.
There’s a DAC tradition on Sunday where you can arrive early and attend a workshop, so Atrenta is offering an IP workshop along with three other companies which highlights how much collaboration is required to be successful:
- Sonics, Inc.
Last year at DAC there was a constant buzz around the Atrenta booth and suites, so I expect that buzz to make a repeat performance at the Moscone Center on June 1st to 4th.
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