WEBINAR: COMPREHENSIVE RTL SIGNOFF BY DESIGNERS USING JASPERGOLD SUPERLINT

WEBINAR: COMPREHENSIVE RTL SIGNOFF BY DESIGNERS USING JASPERGOLD SUPERLINT
by Admin on 06-24-2020 at 8:00 am

Webinar Details

Comprehensive RTL Signoff by Designers Using JasperGold Superlint
Date: Wednesday, June 24, 2020
Time: 08:00 PDT / 17:00 CEST / 18:00 IDT / 20:30 IST

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Send email to: eur_training@cadence.com

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Identifying glitches and revealing the extra power they consume require special attention to cell delays and wire delays. To enable earlier and more frequent analysis, physical-and-timing-aware glitch power analysis is needed throughout the flow from RTL to Signoff. In this webinar, we review the glitch power challenges … Read More


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Today Atrenta and Mentor announced that they were collaborating to enable accurate, signoff quality power estimation at the RTL for entire SoCs. The idea is to facilitate RTL power estimation for designs of over 50M gates running actual software loads over hundreds of millions of cycles, resulting in simulation datasets in the… Read More


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