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Atrenta: Mentor/Spyglass Power Signoff…and a Book

Atrenta: Mentor/Spyglass Power Signoff…and a Book
by Paul McLellan on 05-30-2013 at 7:00 am

 Today Atrenta and Mentor announced that they were collaborating to enable accurate, signoff quality power estimation at the RTL for entire SoCs. The idea is to facilitate RTL power estimation for designs of over 50M gates running actual software loads over hundreds of millions of cycles, resulting in simulation datasets in the 10s of gigabytes.

Under the hood, the implementation is an interface between Mentor’s Veloce2 emulator and SpyGlass Power RTL power estimation tool. This enables estimation of SoC power and validation of power budgets at the full-chip level. This is important since power is actually a chip-level problem (although there are local power issues concerned with thermal and power supplies). The interface files from the emulator differ from files generated by standard RTL simulation tools since they are optimized for large data sets over millions of cycles. SpyGlass power can consume the switching activity interface format (SAIF) generated by Veloce2, as well as files in the industry-standard FSDB format.

The results of this collaboration will be shown in both the Atrenta booth and the Mentor booth during DAC. Atrenta is in booth 1847. Mentor is in booth 2046.

 Also, this week, Atrenta announced the publication of a new book on timing constraints. The book Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) is authored by Sridhar Gangadharan, senior product director at Atrenta and Sanjay Churiwala, director at Xilinx. The book, which features a foreword by Dr. Ajoy Bose, chairman, president and CEO of Atrenta, is being published by Springer Science+Business Media.

The book targets system on chip designers and provides a complete overview of how to create effective timing constraints using SDC, including detailed syntax and semantics, its impact on timing analysis and synthesis and the interaction of timing constraints with the rest of the design flow.

I will review the book on Semiwiki…but after DAC, this week is already too insane.

Springer have a booth at DAC so I’m sure it will be available there (and probably discounted during the show but I’m just guessing). The book is available on Amazon here. Springer is at booth 1243.

Full details of Atrenta activities at DAC, including links for registration, are here. Atrenta is at booth 1847. Atrenta is also the sponsor of the “hot zone” at the DAC party on Monday night.

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