Seminar: 2.5D/3D IC Packaging Verification

Seminar: 2.5D/3D IC Packaging Verification
by Daniel Payne on 11-06-2019 at 10:00 am

Overview

Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this… Read More


Webinar: From HLS Component to a Working Design

Webinar: From HLS Component to a Working Design
by Daniel Payne on 10-15-2019 at 10:00 am

Overview

Complex algorithms do not exist in a vacuum. After HLS is used to create an RTL component, to be useful, it needs to be integrated into a larger system. This means connecting it to other components, a processor, and even software. Once integrated, the system needs to be verified. The verification of the complete environment… Read More


Webinar: Implementing Machine Learning Hardware Using High-Level Synthesis

Webinar: Implementing Machine Learning Hardware Using High-Level Synthesis
by Daniel Payne on 10-08-2019 at 10:00 am

Overview

Neural networks are typically developed and trained in a high-performance 32-bit floating-point compute environment. But, in many cases a custom hardware solution is needed for the inference engine to meet power and real-time requirements. Each neural network and end-application may have different performance… Read More


Seminar: 2.5D/3D IC Packaging Verification

Seminar: 2.5D/3D IC Packaging Verification
by Daniel Payne on 10-02-2019 at 10:00 am

Overview

Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this… Read More


Webinar: Using High-Level Synthesis to Accelerate Computer/Machine Vision Applications

Webinar: Using High-Level Synthesis to Accelerate Computer/Machine Vision Applications
by Daniel Payne on 10-01-2019 at 10:00 am

Overview

HLS has been used in multiple companies, projects, and designs targeting vision processing for the past several years. HLS adoption continues to grow because it is the fastest way to turn complex algorithms into efficient hardware implementations. HLS creates a methodology that enables design teams to rapidly react… Read More


Webinar: Visualizer and Optimizing Questa Performance

Webinar: Visualizer and Optimizing Questa Performance
by Daniel Payne on 09-25-2019 at 11:30 am

Hosted by Oasis Sales and Trilogic, Inc.

Overview

Performance:  Every engineer wants more.  In this seminar we will look at using Questa vopt flow to gain raw simulator performance.  We will also look at how Questa Visualizer brings performance through debug efficiency. Finally we will see how working together, these tools can… Read More


Webinar: Xpedition Product Update for VX.2.6

Webinar: Xpedition Product Update for VX.2.6
by Daniel Payne on 09-25-2019 at 9:00 am

Overview

The VX.2.6 release for Xpedition Enterprise brings a significant update to the core PCB design flow, as well as cross-domain integrations with other Siemens technologies. This session will talk about specific improvements in design capture, layout, data management, and design validation. It will also cover functionality… Read More


Webinar: HLS — What, How and Why Now?

Webinar: HLS — What, How and Why Now?
by Daniel Payne on 09-24-2019 at 10:00 am

Overview

HLS has been around for years, so why are we seeing such growth now? This webinar starts with an introduction of basic HLS concepts, design methodologies, best fits for HLS with customer use cases/highlights that explain the benefits they experienced and their adoption path. It will then move to a discussion of trends … Read More


Webinar: Should I Kill My Formal Run – Part 2: What You Can Do Beforehand to Avoid Trouble and Set Yourself Up for Success

Webinar: Should I Kill My Formal Run – Part 2: What You Can Do Beforehand to Avoid Trouble and Set Yourself Up for Success
by Daniel Payne on 09-24-2019 at 8:00 am

Overview

In this segment we assume you are about to kick off a formal analysis, and want to make sure you will avoid the most obvious pitfalls in setting up your formal testbench, the DUT, and the runner scripting.

What You Will Learn

  • How you can setup your formal testbench for success by writing assertions, constraints, and cover
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Seminar: Mentor Forum for Tessent DFT 2019 India

Seminar: Mentor Forum for Tessent DFT 2019 India
by Daniel Payne on 09-17-2019 at 9:00 am

Overview

Test for the Autonomous Age

The seminar will focus on three key test challenges IC vendors face as they try to make the promises of the autonomous age a reality.

  • Implementing DFT on the very large designs and new compute architectures that are required for efficient AI and machine learning
  • Achieving high test quality and
Read More