Configuration Environment is Make-or-Break for IC Verification

Configuration Environment is Make-or-Break for IC Verification
by Tom Simon on 12-10-2020 at 10:00 am

IC Verification Environment

All semiconductor design work today rests on the three-legged stool of Foundries, EDA Tools and Designers. Close collaboration between the three make possible the successful completion of ever more complex designs, especially those at advanced nodes. Perhaps one of the most critical intersections of all three is during physical… Read More


Verification IP proves essential for PCIe GEN5

Verification IP proves essential for PCIe GEN5
by Tom Simon on 12-08-2020 at 6:00 am

PCIe Verification IP

PCI Express (PCIe) has become an important communication element in a wide range of systems. It is used to connect networking, storage, FPGA and GPGPU boards to servers and desktop systems. It has progressed a long way from its initial parallel bus format. Its evolution to a serial point to point configuration has been accompanied… Read More


A Fast Checking Methodology for Power/Ground Shorts

A Fast Checking Methodology for Power/Ground Shorts
by Tom Dillinger on 12-01-2020 at 10:00 am

Figure 4

The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow.  The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More


How About a Faster Fast SPICE? Much Faster!

How About a Faster Fast SPICE? Much Faster!
by Tom Simon on 07-22-2020 at 10:35 am

Analog FastSPICE eXTreme

When Analog FastSPICE was first introduced in 2006 it changed the landscape for high performance SPICE simulation. During the last 14 years it has been used widely to verify advanced nanometer designs. Of course, since then the most advanced designs have progressed significantly, making verification even more difficult. Just… Read More


The Moving Target Known as UPF

The Moving Target Known as UPF
by Tom Simon on 06-18-2020 at 10:00 am

UPF hierarchy

As if engineers did not have enough difficulty just getting everything right so that their designs are implemented functionally correct, the demands of lowering power consumption require changes that can affect functionality and verification. Techniques such as power gating, clock gating, mixed supply voltage, voltage … Read More


High Speed SerDes Design and Simulation Webinar Replay from Mentor

High Speed SerDes Design and Simulation Webinar Replay from Mentor
by Tom Simon on 05-14-2020 at 10:00 am

Mentor SerDes Simulation

Over the years SerDes (serializer/deserializer) based connections have proliferated into just about every connection within and among computing systems. Years ago, parallel interfaces were the most common method of moving data, but issues of signal integrity, synchronization and power simply became too much for the required… Read More


DFT Innovations Come from Customer Partnerships

DFT Innovations Come from Customer Partnerships
by Tom Simon on 05-05-2020 at 10:00 am

Mentro Tessent Innovation

There is an adage that says that quality is not something that can be slapped on at the end of the design or manufacturing process. Ensuring quality requires careful thought throughout development and production. Arguably this adage is more applicable to the topic of Design for Test (DFT) than almost any other area of IC development… Read More


Learning to Live with the Gaps Between Design and Verification

Learning to Live with the Gaps Between Design and Verification
by Tom Simon on 04-09-2020 at 6:00 am

Learning to live with the gaps between design and verification

Whenever I am asked to explain how chip design works by someone who is unfamiliar with the process, I struggle to explain the different steps in the flow. It also makes me aware of the discrete separations between each phase of activities. Of course, when you speak to a novice it is not even possible to get more than one layer down in the… Read More


Bringing Hierarchy to DFT

Bringing Hierarchy to DFT
by Tom Simon on 01-30-2020 at 6:00 am

Tessent Hierarchical Flow

Hierarchy is nearly universally used in the SoC design process to help manage complexity. Dealing with flat logical or physical designs proved unworkable decades ago. However, there were a few places in the flow where flat tools continued to be used. Mentor lead the pack in the years around 1999 in helping the industry move from … Read More