EDA in the Cloud – Now More Than Ever

EDA in the Cloud – Now More Than Ever
by Kalar Rajendiran on 07-27-2021 at 10:00 am

Screen Shot 2021 07 14 at 4.32.16 PM

A decade ago, many of us heard commentaries on how entrepreneurs were turned down by venture capitalists for not including a cloud strategy in their business plan, no matter what the core business was. Humorous punchlines such as, “It’s cloudy without any clouds” and “Add some cloud to your strategy and your future will be bright… Read More


Developing Verification Flows for Silicon Photonics

Developing Verification Flows for Silicon Photonics
by Tom Simon on 05-13-2021 at 10:00 am

Silicon Photonics DRC

Silicon photonics is getting a lot of interest because it can be used in many applications to improve bandwidth, reduce power and provide novel new functionality. It is especially interesting because it offers an ability to combine electronics and optical elements into the same die. Though it is fabricated with familiar silicon… Read More


Probing UPF Dynamic Objects

Probing UPF Dynamic Objects
by Tom Simon on 01-28-2021 at 6:00 am

Probing UPF Dynamic Objects

UPF was created to go beyond what HDL can do for managing on-chip power. HDLs are agnostic when it comes to dealing with supply & ground connections, power domains, level shifters, retention and other power management related elements of SoCs. UPF fills the breach allowing designers to specify in detail what parts of the design… Read More


Configuration Environment is Make-or-Break for IC Verification

Configuration Environment is Make-or-Break for IC Verification
by Tom Simon on 12-10-2020 at 10:00 am

IC Verification Environment

All semiconductor design work today rests on the three-legged stool of Foundries, EDA Tools and Designers. Close collaboration between the three make possible the successful completion of ever more complex designs, especially those at advanced nodes. Perhaps one of the most critical intersections of all three is during physical… Read More


Lowering your PCB Costs through Panelization

Lowering your PCB Costs through Panelization
by Admin on 12-09-2020 at 12:00 am

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Online – Dec 9, 2020
11:00 AM – 12:00 PM US/Eastern
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Overview

One area that can save significant cost that many designers and managers don’t consider is designing your own PCB panels. You can learn from an expert how to get more efficient use out of the available

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Verification IP proves essential for PCIe GEN5

Verification IP proves essential for PCIe GEN5
by Tom Simon on 12-08-2020 at 6:00 am

PCIe Verification IP

PCI Express (PCIe) has become an important communication element in a wide range of systems. It is used to connect networking, storage, FPGA and GPGPU boards to servers and desktop systems. It has progressed a long way from its initial parallel bus format. Its evolution to a serial point to point configuration has been accompanied… Read More


Embedded Software Debug Using Integrated Codelink and Visualizer HW/SW Debug Environment

Embedded Software Debug Using Integrated Codelink and Visualizer HW/SW Debug Environment
by Admin on 12-08-2020 at 12:00 am

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Online – Dec 8, 2020
8:00 AM – 9:00 AM US/Pacific
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Overview

Intuitive and easy to use, Codelink Software Debug Environment automates debugging for embedded software and correlates embedded software and hardware debug of complex SoC’s.

During debug, Visualizer

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MEMS Digital Qualification – Predicting Yield During Initial Design

MEMS Digital Qualification – Predicting Yield During Initial Design
by Admin on 12-03-2020 at 12:00 am

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Online – Dec 3, 2020
9:00 AM – 10:00 AM US/Pacific
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Online – Dec 3, 2020
5:00 PM – 6:00 PM US/Pacific
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Overview

In MEMS and semiconductor design, 20% of the upstream design decisions affect 80% of the downstream foundry

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A Fast Checking Methodology for Power/Ground Shorts

A Fast Checking Methodology for Power/Ground Shorts
by Tom Dillinger on 12-01-2020 at 10:00 am

Figure 4

The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow.  The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More


Secure Mobility Vitals: Transport Layer Security (TLS) and Firewall

Secure Mobility Vitals: Transport Layer Security (TLS) and Firewall
by Admin on 11-24-2020 at 12:00 am

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Online – Nov 24, 2020
14:00 – 15:00 Europe/London
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Overview

This presentation will cover remote access requirements of connected vehicles, an internet-based threat analysis and design considerations for TLS and firewall. Practical examples from in-production

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