Five Key Workflows For 3D IC Packaging Success

Five Key Workflows For 3D IC Packaging Success
by Kalar Rajendiran on 08-31-2022 at 6:00 am

3D IC design workflows

An earlier blog started with the topic of delivering 3D IC innovations faster. The blog covered the following foundational enablers for successful heterogeneous 3D IC implementation.

  • System Co-Optimization (STCO) approach
  • Transition from design-based to systems-based optimization
  • Expanding the supply chain and tool
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Delivering 3D IC Innovations Faster

Delivering 3D IC Innovations Faster
by Kalar Rajendiran on 08-16-2022 at 6:00 am

System Technology Co Optimization STCO

3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic of discussion. The technology was originally leveraged for stacking functional blocks with high-bandwidth buses between them. Memory manufacturers and other IDMs were the ones to typically leverage this … Read More


The Semiconductor Ecosystem Explained

The Semiconductor Ecosystem Explained
by Steve Blank on 02-06-2022 at 6:00 am

TSMC Ecosystem Explained

The last year has seen a ton written about the semiconductor industry: chip shortages, the CHIPS Act, our dependence on Taiwan and TSMC, China, etc.

But despite all this talk about chips and semiconductors, few understand how the industry is structured. I’ve found the best way to understand something complicated is to diagram… Read More


EDA in the Cloud – Now More Than Ever

EDA in the Cloud – Now More Than Ever
by Kalar Rajendiran on 07-27-2021 at 10:00 am

Screen Shot 2021 07 14 at 4.32.16 PM

A decade ago, many of us heard commentaries on how entrepreneurs were turned down by venture capitalists for not including a cloud strategy in their business plan, no matter what the core business was. Humorous punchlines such as, “It’s cloudy without any clouds” and “Add some cloud to your strategy and your future will be bright… Read More


Developing Verification Flows for Silicon Photonics

Developing Verification Flows for Silicon Photonics
by Tom Simon on 05-13-2021 at 10:00 am

Silicon Photonics DRC

Silicon photonics is getting a lot of interest because it can be used in many applications to improve bandwidth, reduce power and provide novel new functionality. It is especially interesting because it offers an ability to combine electronics and optical elements into the same die. Though it is fabricated with familiar silicon… Read More


Probing UPF Dynamic Objects

Probing UPF Dynamic Objects
by Tom Simon on 01-28-2021 at 6:00 am

Probing UPF Dynamic Objects

UPF was created to go beyond what HDL can do for managing on-chip power. HDLs are agnostic when it comes to dealing with supply & ground connections, power domains, level shifters, retention and other power management related elements of SoCs. UPF fills the breach allowing designers to specify in detail what parts of the design… Read More


Configuration Environment is Make-or-Break for IC Verification

Configuration Environment is Make-or-Break for IC Verification
by Tom Simon on 12-10-2020 at 10:00 am

IC Verification Environment

All semiconductor design work today rests on the three-legged stool of Foundries, EDA Tools and Designers. Close collaboration between the three make possible the successful completion of ever more complex designs, especially those at advanced nodes. Perhaps one of the most critical intersections of all three is during physical… Read More


Verification IP proves essential for PCIe GEN5

Verification IP proves essential for PCIe GEN5
by Tom Simon on 12-08-2020 at 6:00 am

PCIe Verification IP

PCI Express (PCIe) has become an important communication element in a wide range of systems. It is used to connect networking, storage, FPGA and GPGPU boards to servers and desktop systems. It has progressed a long way from its initial parallel bus format. Its evolution to a serial point to point configuration has been accompanied… Read More


A Fast Checking Methodology for Power/Ground Shorts

A Fast Checking Methodology for Power/Ground Shorts
by Tom Dillinger on 12-01-2020 at 10:00 am

Figure 4

The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow.  The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More