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Register Transfer Level (RTL) power analysis, performed early in the design cycle, is a key component of end-to-end methodology to maximize energy efficiency. Such analysis has become a critical requirement for many IC designs today and in the future. Although RTL power analysis technology… Read More
Near the end of any large SoC design project, the RTL code is nearly finished, floorplanning has been done, place and route has a first-pass, static timing has started, but the timing and power goals aren’t met. So, iteration loops continue on blocks and full-chip for weeks or even months. It could take a design team 5-7 days… Read More
After almost three decades in the EDA business, it is beyond my comprehension to understand why chip designers still hand-write RTL for complex register maps – chip designs with hundreds of registers and thousands of register fields. In today’s silicon world where software is the key to chip-based product success, it is the register… Read More
Date: Thursday, September 22, 2022
Time: 12:00pm – 1:00pm (PDT)
As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging… Read More
The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart… Read More
The hardware/software interface, or HSI is the critical piece of technology that allows software to communicate with the hardware it’s controlling.
With all the dedicated processors in most designs today, this is a very important part of the architecture. If it doesn’t work, the product doesn’t ship. If it has a subtle bug, new… Read More
Standards help our EDA and IP industry grow more quickly and with less CAD integration efforts, and IP-XACT is another one of those Accellera standards (1685-2009) that is coming of age, and enabling IP reuse for SoC design teams. Here at SemiWik, we’ve been writing about Defacto Technologies and their prominent use of IP-XACT… Read More
I read the semiconductor press, LinkedIn and social media (Twitter, Facebook) every morning along with an RSS feed that I setup, staying current on everything related to using EDA tools to make the task of SoC design a bit easier for design teams. A recent press release announced a tool called SoC Compiler, so my curiosity was piqued… Read More
Arm and Mentor Recently announced that the Arm Design Reviews program now offers Mentor help in verification design reviews. I talked to Paul Williams (Sr Consultant and Verification Practice Lead at Mentor Graphics) and Peter Lewin (Dir. Mktg at Arm Partner Enablement Group) to get more insight into Arm Design Services, particularly… Read More
