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Magillem offers a practical UPF power flow

Magillem offers a practical UPF power flow
by Tom Simon on 05-28-2019 at 10:00 am
Categories: Uncategorized

We already know that IP-Xact is extremely useful for managing IP and SOC design specifications, yet it may come as a surprise to learn that it also can be used to form the basis of a power flow too. There are design tools that read UPF to help implement and verify designs, however it can be extremely useful to understand the interplay … Read More

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The Practice of Low Power Design

The Practice of Low Power Design
by Bernard Murphy on 11-14-2017 at 7:00 am
Categories: Cadence, EDA
1 Comment

For any given design objective, there is what we in the design automation biz preach that design teams should do, and then there’s what designs teams actually do. For some domains, the gap between these two may be larger than others, but we more or less assume that methodologies which have been around for years and are considered to… Read More

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Clock Gating Optimization

Clock Gating Optimization
by Bernard Murphy on 09-21-2017 at 7:00 am
Categories: EDA, Synopsys

You can save a lot of power in a design by gating clocks. For much of the time in a complex multi-function design, many (often most) of the clocks are toggling registers whose input values aren’t changing. Which means that those toggles are changing nothing functionally yet they are still burning power. Why not turn off those clock… Read More

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Analysis and Signoff for Restructuring

Analysis and Signoff for Restructuring
by Bernard Murphy on 08-29-2017 at 7:00 am
Categories: Defacto Technologies, EDA

For the devices we build today, design and implementation are unavoidably entangled. Design for low-power, test, reuse and optimized layout are no longer possible without taking implementation factors into account in design, and vice-versa. But design teams can’t afford to iterate indefinitely between these phases, so they… Read More

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Open-Silicon Update: 125M ASICs shipped!

Open-Silicon Update: 125M ASICs shipped!
by Daniel Nenni on 02-03-2017 at 12:00 pm
Categories: IoT, Open-Silicon, Semiconductor Services

As you all know I am a big fan of the ASIC business model. It was critical in the transformation of the fabless semiconductor industry and still plays a critical part in our success. In fact, the ASIC business model is leading the way for systems companies to make their own chips. Remember, Apple started with the ASIC business model … Read More

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How ARM designs and optimizes SoCs for low-power

How ARM designs and optimizes SoCs for low-power
by Daniel Payne on 12-19-2016 at 12:00 pm
Categories: ARM, EDA, IP, Mentor, a Siemens Business

ARM has become such a worldwide powerhouse in delivering processors to the semiconductor IP market because they have done so many things well: IP licensing model, variety, performance, and low-power. On my desk are two devices with ARM IP, a Samsung Galaxy Note 4 smart phone and a Google tablet. Most of my readers will likely have… Read More

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How to nail your PPA tradeoffs

How to nail your PPA tradeoffs
by Beth Martin on 11-03-2016 at 4:00 pm
Categories: EDA, Mentor, a Siemens Business

Image RemovedHow do you ensure your design has been optimized for power, performance, and area? I posed this question to Mentor’s Group Director of Marketing, Sudhakar Jilla and product specialist Mark Le. They said that finding the PPA sweet spot is still often done by trial and error – basically serial experiments with various… Read More

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Achieving Lower Power through RTL Design Restructuring (webinar)

Achieving Lower Power through RTL Design Restructuring (webinar)
by Daniel Payne on 10-18-2016 at 4:00 pm
Categories: Defacto Technologies, EDA, Events

From a consumer viewpoint I want the longest battery life from my electronic devices: iPad tablet, Galaxy Note 4 smart phone, Garmin Edge 820 bike computer, and Amazon Kindle book reader. In September I blogged about RTL Design Restructuring and how it could help achieve lower power, and this month I’m looking forward to … Read More

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A Credible Player at the Power Table

A Credible Player at the Power Table
by Bernard Murphy on 08-03-2016 at 7:00 am
Categories: IoT, Mentor, a Siemens Business, Mobile

For a while it seemed like Mentor lived on the margins of the (RTL) design-for-power game. They had interesting Image Removedmicro-architectural optimization capabilities through their Calypto heritage but no real industry chops in power estimation, a must-have when you are claiming to reduce power. Better known offerings… Read More

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High Level Synthesis Update

High Level Synthesis Update
by Tom Dillinger on 06-29-2016 at 7:00 am
Categories: EDA, Mentor, a Siemens Business

High-level synthesis (HLS) involves the generation of an RTL hardware model from a C/C++/SystemC description. The C code is typically referred to as abehavioraloralgorithmicmodel. The C language constructs and semantics available to architects enable efficient and concise coding – the code itself is smaller, easier to write/read,… Read More