Using IP-XACT, RTL and UPF for Efficient SoC Design

Using IP-XACT, RTL and UPF for Efficient SoC Design
by Daniel Payne on 06-30-2022 at 6:00 am

ESDA Revenue

The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart… Read More


Introduction to the Joules RTL Power Solution

Introduction to the Joules RTL Power Solution
by Admin on 03-08-2022 at 12:00 am

08 Mar 2022

Online

Event Details

Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow?

Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar.

Built on a multi-threaded frame-based architecture, the Cadence

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Three Perspectives on the Hardware/Software Interface – Who’s Right?

Three Perspectives on the Hardware/Software Interface – Who’s Right?
by Daniel Nenni on 03-01-2022 at 10:00 am

The hardware/software interface, or HSI is the critical piece of technology that allows software to communicate with the hardware it’s controlling.

With all the dedicated processors in most designs today, this is a very important part of the architecture. If it doesn’t work, the product doesn’t ship. If it has a subtle bug, new… Read More


Webinar – How to manage IP-XACT complexity in conjunction with RTL implementation flow

Webinar – How to manage IP-XACT complexity in conjunction with RTL implementation flow
by Daniel Payne on 10-26-2021 at 10:00 am

RTL Integration

Standards help our EDA and IP industry grow more quickly and with less CAD integration efforts, and IP-XACT is another one of those Accellera standards (1685-2009) that is coming of age, and enabling IP reuse for SoC design teams. Here at SemiWik, we’ve been writing about Defacto Technologies and their prominent use of IP-XACT… Read More


Small EDA Company with Something New: SoC Compiler

Small EDA Company with Something New: SoC Compiler
by Daniel Payne on 04-26-2021 at 10:00 am

Defacto SoC Compiler

I read the semiconductor press, LinkedIn and social media (Twitter, Facebook) every morning along with an RSS feed that I setup, staying current on everything related to using EDA tools to make the task of SoC design a bit easier for design teams. A recent press release announced a tool called SoC Compiler, so my curiosity was piqued… Read More


Arm Design Reviews add Mentor for Verification Review

Arm Design Reviews add Mentor for Verification Review
by Bernard Murphy on 10-27-2020 at 6:00 am

Arm Design Reviews

Arm and Mentor Recently announced that the Arm Design Reviews program now offers Mentor help in verification design reviews. I talked to Paul Williams (Sr Consultant and Verification Practice Lead at Mentor Graphics) and Peter Lewin (Dir. Mktg at Arm Partner Enablement Group) to get more insight into Arm Design Services, particularly… Read More


The Polyglot World of Hardware Design and Verification

The Polyglot World of Hardware Design and Verification
by Daniel Nenni on 07-23-2020 at 10:00 am

SemiWiki article

It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More


Complete RTL to GDSII Flow for “Analog on Top” Designs

Complete RTL to GDSII Flow for “Analog on Top” Designs
by Admin on 06-29-2020 at 9:00 am

Register For This Web Seminar

Online – Jun 29, 2020
9:00 AM – 10:00 AM US/Pacific
Online – Jun 29, 2020
5:00 PM – 6:00 PM US/Pacific

Overview

Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and

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Complete RTL to GDSII Flow for “Analog on Top” Designs

Complete RTL to GDSII Flow for “Analog on Top” Designs
by Admin on 06-29-2020 at 9:00 am

Register For This Web Seminar

Online – Jun 29, 2020
9:00 AM – 10:00 AM US/Pacific

Online – Jun 29, 2020
5:00 PM – 6:00 PM US/Pacific

Overview

Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and

Read More

Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
by Mike Gianfagna on 06-16-2020 at 6:00 am

Screen Shot 2020 06 15 at 6.59.34 PM

I had the opportunity to preview an upcoming webinar from Synopsys on SoC Glitch Power – what it is and how to reduce it. There is some eye-opening information in this webinar. Glitch power is a bigger problem than you may think and Synopsys has some excellent strategies to help reduce the problem. The webinar is available via replay… Read More