Afraid of mesh-based clock topologies? You should be

Afraid of mesh-based clock topologies? You should be
by Daniel Payne on 03-18-2024 at 10:00 am

mesh-based clock topology

Digital logic chips synchronize all logic operations by using a clock signal connected to flip-flops or latches, and the clock is distributed across the entire chip. The ultimate goal is to have a clock signal that arrives at the exact same moment in time at all clocked elements. If the clock arrives too early or too late from the PLL… Read More


Webinar: RTL-to-GDSII Flow for ASIC Design Using Cadence Tools

Webinar: RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
by Admin on 11-28-2023 at 4:46 pm

Would you like to know how to design a complete chip using the RTL-to-GDSII Flow?

In this free technical Training Webinar with Application Engineer Sai Srinivas Pamula, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator,… Read More


Handling metastability during Clock Domain Crossing (CDC)

Handling metastability during Clock Domain Crossing (CDC)
by Daniel Payne on 11-22-2023 at 10:00 am

synchronizer min

SoC designs frequently have lots of different clock domains to help manage power more efficiently, however one side effect is that when the clock domains meet, i.e., in a Clock Domain Crossing (CDC), there’s the possibility of setup and hold time violations that can cause a flip-flop to become metastable. Synchronizer … Read More


Webinar: RTL Power Optimization: Applying Best Practices to Overcome Low-Power Design Challenges

Webinar: RTL Power Optimization: Applying Best Practices to Overcome Low-Power Design Challenges
by Admin on 10-25-2023 at 2:43 pm

Designers face enormous challenges for low-power designs. Whether it is IoT at the edge, AI in the datacenter, robotics or ADAS, the demand for increased functionality in SoCs is rapidly outpacing the power budget. Power must be considered at every stage of chip design including performance, reliability and packaging. Waiting

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Webinar: A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores

Webinar: A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
by Admin on 07-13-2023 at 9:27 pm

Wednesday, July 26, 2023 | 10:00 a.m. – 11:00 a.m. PDT

RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased

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Webinar: Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise

Webinar: Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
by Admin on 06-30-2023 at 2:58 pm

Synopsys Webinar | Thursday, July 20, 2023 | 10:00 a.m. – 11:00 a.m. Pacific

As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc.,

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Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers

Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers
by Admin on 06-20-2023 at 4:18 pm

As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source.

This webinar covers comprehensive static verification capabilities… Read More


Webinar: Achieving Consistent RTL Power Analysis Accuracy

Webinar: Achieving Consistent RTL Power Analysis Accuracy
by Admin on 12-15-2022 at 3:56 pm

*Company email required for registration*

Register Transfer Level (RTL) power analysis, performed early in the design cycle, is a key component of end-to-end methodology to maximize energy efficiency. Such analysis has become a critical requirement for many IC designs today and in the future. Although RTL power analysis technology… Read More


SoC Design Closure Just Got Smarter

SoC Design Closure Just Got Smarter
by Daniel Payne on 11-08-2022 at 10:00 am

iterations min

Near the end of any large SoC design project, the RTL code is nearly finished, floorplanning has been done, place and route has a first-pass, static timing has started, but the timing and power goals aren’t met. So, iteration loops continue on blocks and full-chip for weeks or even months. It could take a design team 5-7 days… Read More