The Polyglot World of Hardware Design and Verification

The Polyglot World of Hardware Design and Verification
by Daniel Nenni on 07-23-2020 at 10:00 am

SemiWiki article

It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More


Complete RTL to GDSII Flow for “Analog on Top” Designs

Complete RTL to GDSII Flow for “Analog on Top” Designs
by Admin on 06-29-2020 at 9:00 am

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Register For This Web Seminar

Online – Jun 29, 2020
9:00 AM – 10:00 AM US/Pacific
Online – Jun 29, 2020
5:00 PM – 6:00 PM US/Pacific

Overview

Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and

Read More

Complete RTL to GDSII Flow for “Analog on Top” Designs

Complete RTL to GDSII Flow for “Analog on Top” Designs
by Admin on 06-29-2020 at 9:00 am

14 thumbnail

Register For This Web Seminar

Online – Jun 29, 2020
9:00 AM – 10:00 AM US/Pacific

Online – Jun 29, 2020
5:00 PM – 6:00 PM US/Pacific

Overview

Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and

Read More

Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
by Mike Gianfagna on 06-16-2020 at 6:00 am

Screen Shot 2020 06 15 at 6.59.34 PM

I had the opportunity to preview an upcoming webinar from Synopsys on SoC Glitch Power – what it is and how to reduce it. There is some eye-opening information in this webinar. Glitch power is a bigger problem than you may think and Synopsys has some excellent strategies to help reduce the problem. The webinar is available via replay… Read More


Magillem offers a practical UPF power flow

Magillem offers a practical UPF power flow
by Tom Simon on 05-28-2019 at 10:00 am

We already know that IP-Xact is extremely useful for managing IP and SOC design specifications, yet it may come as a surprise to learn that it also can be used to form the basis of a power flow too. There are design tools that read UPF to help implement and verify designs, however it can be extremely useful to understand the interplay … Read More


The Practice of Low Power Design

The Practice of Low Power Design
by Bernard Murphy on 11-14-2017 at 7:00 am

For any given design objective, there is what we in the design automation biz preach that design teams should do, and then there’s what designs teams actually do. For some domains, the gap between these two may be larger than others, but we more or less assume that methodologies which have been around for years and are considered to… Read More


Clock Gating Optimization

Clock Gating Optimization
by Bernard Murphy on 09-21-2017 at 7:00 am

You can save a lot of power in a design by gating clocks. For much of the time in a complex multi-function design, many (often most) of the clocks are toggling registers whose input values aren’t changing. Which means that those toggles are changing nothing functionally yet they are still burning power. Why not turn off those clock… Read More


Analysis and Signoff for Restructuring

Analysis and Signoff for Restructuring
by Bernard Murphy on 08-29-2017 at 7:00 am

For the devices we build today, design and implementation are unavoidably entangled. Design for low-power, test, reuse and optimized layout are no longer possible without taking implementation factors into account in design, and vice-versa. But design teams can’t afford to iterate indefinitely between these phases, so they… Read More


Open-Silicon Update: 125M ASICs shipped!

Open-Silicon Update: 125M ASICs shipped!
by Daniel Nenni on 02-03-2017 at 12:00 pm

As you all know I am a big fan of the ASIC business model. It was critical in the transformation of the fabless semiconductor industry and still plays a critical part in our success. In fact, the ASIC business model is leading the way for systems companies to make their own chips. Remember, Apple started with the ASIC business model … Read More


How ARM designs and optimizes SoCs for low-power

How ARM designs and optimizes SoCs for low-power
by Daniel Payne on 12-19-2016 at 12:00 pm

ARM has become such a worldwide powerhouse in delivering processors to the semiconductor IP market because they have done so many things well: IP licensing model, variety, performance, and low-power. On my desk are two devices with ARM IP, a Samsung Galaxy Note 4 smart phone and a Google tablet. Most of my readers will likely have… Read More