In the early days of Customer Owned Tooling (COT) the signoff was done at the GDS II, or physical level. Today, however we see the trend of RTL signoff instead because of the EDA tools and methodology available. At DACearlier this month I met with Piyush Sanchetiof Atrenta to get an update on what’s new with RTL signoff.
Q: What is your background in EDA?
I have run product marketing at Atrenta since 2010, joined in 2005 and did business development and sales, Mike Gianfangna managed corporate marketing (then moved to eSilicon). Before that I was at Sequence (now apache), Sente (acquired by Sequence) and Cadence.
Q: What’s new with RTL signoff?
At the last DAC “RTL Signoff” was launched. As designs are more complex you now need a new methodology to ensure success. Signoff for IP is now morphing to SoC signoff at RTL level.
With a few hundred million gates now possible, engineers are doing block-level design and re-using IP from companies like ARM and many others. Then SoC integrators must assemble and verify proper operation. Block designers and SoC integrators are two separate groups.
Q: What is new for this year at Atrenta?
In the past 12 months we announced a hierarchical abstraction approach, which enables RTL signoff. Each IP block goes through signoff, then with hierarchy we can do chip-level signoff. This hierarchy approach makes RTL signoff run quickly and within a reasonable amount of RAM.
Managing a complete SoC is now feasible with hierarchy (Hierarchical SoC Abstraction – new option). The divide and conquer approach is well understood in the SoC design flow, so it has been well adopted.
On the IP front we’ve added the verification component. Two years ago we acquired NextOp software and it’s BugScope product,which is focused on dynamic verification, and making assertion based verification more automated. Adding more assertions makes your design stronger because any violation gets triggered. Functional coverage also quantifies how well the design has been verified. Manual assertions are difficult to verify, so BugScopebrings more automated generation of assertions and functional coverage. This makes for a more rounded RTL verification platform, as BugScope brings in functional or dynamic coverage.
Q: How are the Atrenta tools supported?
There is a direct sales force and AEs in the world geographies (Taiwan, China, Israel, India, Japan, USA, Europe). This team helps engineers learn the tools. We also have online training with videos that are short and directed, about 60-70 videos now, and access to the content requires a portal login. Expect the video library to grow to hundreds by end of year.
Q: What is the Atrenta position versus competitors?
Competitors do offer some point tools, but nothing as broad as Atrenta in RTL signoff. We work well with Cadence, Synopsys and Mentor tool flows, as they all support an RTL flow. Calypto and RealIntent compete on point tools, so it keeps our tools competitive.
We offer a multi-functional platform that can perform cross-domain analysis, for example optimizing the design for power with clock gating without violating clock domain crossing. You cannot do this with separate tools for power and CDC.
Q: How would you measure success by 2015?
We had 63% growth in new business this last year, versus 37% repeat business. We expect about a 25% revenue growth in our business this year. We want to see two back-to-back years in high growth. An IPO is always possible. Scaling in EDA has always been a challenge to get beyond the $10M barrier, the $50M barrier, and so on. Going public is not an end in itself, because you now have quarterly targets to hit.
Q: Does Atrenta have tools in the TSMC reference flows?
TSMC reference flows are more physical implementation centric, we have been in their IP9000 program for three years, and are part of their soft-IP program. Atrenta and TSMC have a set of golden rules that new soft IP partners use and then report to TSMC. The IP partners must pass this level of Atrenta testing. We did a workshop on Sunday at DAC for this topic.
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