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Atrenta CEO on RTL Signoff

Atrenta CEO on RTL Signoff
by Daniel Nenni on 05-16-2013 at 9:00 pm

Most EDA companies sell tools into the main chip design and implementation flow such as simulation, synthesis, place & route, custom design and mask data prep. Atrenta is different. Nothing the company sells is in this main design flow. Instead, Atrenta focuses on pre-synthesis design analysis and optimization. Everything associated with developing RTL that is implementation-ready. Atrenta’s DAC story is all about RTL signoff. I recently met with Atrenta’s CEO, Dr. Ajoy Bose to find out more about Atrenta’s unusual place in the design flow and what RTL signoff really means.

Q: What design challenges does Atrenta address?
There are two primary themes here – complexity and time-to-market.
Complexity challenges result from very large SoCs pushing the limits on design size, number of IPs, power, performance, etc. These designs are typically targeted for applications such as smartphones, tablets, networking and graphics.

Time-to-market challenges result from mid to small size designs targeting applications such as automotive, consumer, industrial automation and medical devices. These are not very complex designs but they require a very quick turnaround, with design cycles in the order of 2-3 months.

There are many ways to address these problems, but we’ve found one of the most powerful methods is to find and fix as many issues as possible at RTL, before detailed implementation begins. Problems such as routing congestion or low test coverage can be found and fixed in a matter of hours with the right tools at RTL. Those same problems take many weeks to find and fix if you’re in a gate-level implementation flow. The benefits are clear.

Q: What specific problems can you find and fix at RTL?

There are many. With our SpyGlass product, we can analyze an RTL design across many domains. Most customers start with LINT. This analysis will find basic errors in the design, such as power connected to ground or unconnected nets. It will also flag RTL structures that can give synthesis tools a hard time, or ones that will cause synthesis/simulation mismatches. We also have an advanced LINT tool that uses formal technology to look deeper into the design for things like unreachable states in a finite state machine.

We also use formal technology to prove that clock domain crossing circuits will perform correctly. This is a very popular product, since CDC bugs are very hard to find in simulation and can either kill a chip or increase its field failure rate. Power is another important area for SpyGlass. The tool will verify CPF/UPF files for correctness, estimate power consumption and recommend ways to reduce power for both logic and memory. We’ll even make circuit changes automatically if desired and use a sequential equivalence tool to prove the circuit functions the same after power reduction.

SpyGlass also looks at timing constraints and ensures they are correct and consistent. We use formal technology again to prove that false and multi-cycle paths have been correctly identified. We also help with estimating test coverage and helping to improve it, both for stuck-at as well as at-speed testing. SpyGlass also helps to reduce physical design challenges such as routing congestion.

On the functional verification front, we recently added a new tool called BugScope which automatically generates assertions. This technology helps determine if there are any coverage holes in the verification plan and creates correct-by-construction assertions to help with debug.

The last part of our tool suite comes from GenSys – a chip assembly environment that automates RTL assembly and re-structuring. We find every design needs to be modified for things like test or power planes, added logic or logical/physical hierarchy divergence, etc. These tasks are very time-consuming and error-prone. GenSys makes them all easy to do.

Q: You talk about RTL signoff in your DAC positioning this year – what does that mean?
We define RTL signoff as a design flow that has “must pass” requirements for the RTL such that the design will not be moved to the next stage of implementation until those requirements are verified. It provides very high confidence that the design is robust, implementable and will meet the design goals. The growing use of “must pass” design flows is an indicator of the maturity of the RTL design process. We’ve seen a growing proliferation of these flows over the past couple of years. I think 28nm and below is driving the trend. The complexity of those designs demands air-tight RTL before hand-off to implementation and an RTL signoff flow is the easiest way to achieve that result.

Q: Who uses RTL signoff flows?

There are really two primary areas of use. First, at the IP level. Here, you want to ensure that your IP choices will work in the final design in a predictable way. There is a lot of analysis around the quality and completeness of the IP deliverables. The goal is to minimize iterations between IP development/procurement and SoC assembly. The soft IP qualification work that Atrenta is doing with TSMC is an example of this use model.

The second area is at SoC assembly. Here, you want to ensure that your design will meet its power, performance and area requirements when implemented. The goal is to minimize iterations between SoC assembly and back-end implementation. The entire design is checked at this stage, so files can be very large. We’re deploying more hierarchical capabilities to address this issue.

Q: What will Atrenta be doing at DAC?
As you mentioned, RTL signoff is a major focus area for us this year. We’ll be hosting interviews in the RTL Signoff Theater in our booth where customers and partners will discuss their experiences with RTL signoff flows. We’ll also have detailed presentations for all our products in our suites.

There are three Designer Track presentations that discuss hierarchical CDC verification, structured assembly and 3D design. Atrenta will be quite visible at the main DAC party on Monday evening as well as a special, invitation-only party on Tuesday evening. You’ll have to come to DAC to learn more about those activities.

Q: Where can our readers find out more about Atrenta at DAC?
Easy, just go to There are prominent links on the home page where you can learn more about our product sessions and sign up for one. You can also find out what other activities we’re involved in at DAC. I hope to see many of your readers at the show.

Also Read:

Sanjiv Kaul is New CEO of Calypto

CEO Interview: Jason Xing of ICScape Inc.

CEO Interview: Jens Andersen of Invarian

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