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CEO Interview: Jens Andersen of Invarian

CEO Interview: Jens Andersen of Invarian
by Daniel Nenni on 05-19-2013 at 9:10 pm

 invarianInvarian is an interesting EDA company that sees a niche market opening in the physical verification space. There are a number of converging factors driving this opportunity. Electromigration and voltage-drop for full-chip analysis demands SPICE level accuracy with fast runtimes. Invarian solves that problem with macro modeling and a parallel architecture. Not only are runtimes greatly reduced, but accuracy is improved by incorporating thermal effects within the overall concurrent analysis flow. It seems like everything is going 3D these days, from FinFETs to heterogeneous stacked-die packaging. In a 3D world thermal effects have a major impact on power, performance and reliability. I got a chance to sit down with Invarian’s CEO, Jens Andersen, and delve into this interesting little company. We have been friends for years so I really enjoyed catching up.

What are some specific customer IC design issues your customers are facing?

  • Our industry is facing the proverbial horns of a dilemma, exponential growth in complexity in one hand and shrinking margins of error in the other. The growth in gate-count is not the problem (Moore’s Law has been with us for some time) but rather the constraints on power consumption, electromigration issues, instantaneous voltage-drop analysis and thermal effects. Sign-off has become so burdened with Band-Aid patches over the years. The cumulative effect has been to create a cumbersome and disjointed process. It has created what I call a time dilation effect. There is simply not enough time for getting simulation runs through the pipe. This is the road to ruin, leading one down a path of unpleasant trade-offs, between incomplete analyses or missing the veritable market window.
  • Our customers are demanding new tools, and for a variety of reasons these tools must be built from the ground up, to handle the complexities of cutting edge processes and large design files, but they must also be easy to setup, use and maintain.
  • Current tools sets are inadequate, in the sense that they do not account for the interaction between thermal, power, timing and voltage. A scenario where each leg of the flow works properly, yet the chip fails catastrophically is entirely within the realm of the possible. In fact, it is a very likely result. The Law of Large Numbers has a nasty habit of punishing gamblers, whether in a casino or at a workstation. It would be folly to expect customers to risk $millions on processes that use blindly set constraints for sign-off.
  • Our customers are now able to model with very accurate results due to our concurrent methodology. Not only do we provide the accuracy necessary to ensure proper chip behavior, we do so with advanced techniques that vastly improve runtime. Without incurring risk or impacting the schedule, our overall goal is to tape-out optimum designs. We aim for just enough margins but not more than enough.
  • There is a Catch-22 when it comes to designs at advanced process nodes. It has always been the case that a process is in flux at an early stage of development. This variation keeps growing as a percentage. That is not the problem. The deviation of the actual versus the predicted has major consequences for other reasons. What has changed and why it is a major issue now, when in the past it could be handled, is that chip evolution has reached the stage where interrelated forces can no longer be neglected. Electromigration and leakage current rely on current density values and thermal effects. Power budgets are set early in the design flow with appropriate clock speeds for meeting performance specs. Transient effects and ground bounce are a constant source of potential error. It’s getting harder to tell the signals from the noise.
  • We developed easy-to-use software and leverage the proven strength of industry standard file formats. There is no need to pre-characterize data with predefined corners. That approach leads to average values that are not accurate for transient analysis. Our concurrent engines allow users the ability to know exactly the condition of their design.
  • Fragmented solutions on the market tend to confound the designer and do not model the physically correct design state. With a muddled mess of average estimations there is no choice but to fall back to worst-case scenarios. There is a penalty with this overkill approach to design. Knowledge is power.
  • We have developed algorithms that keep our concurrent analysis engines in sync to provide extremely accurate data. Our results have been correlated with true physical measurements with amazing accuracy.What does Invarian do?
    We have a dual focus:
  • Our primary focus is our InVar Pioneer Platform consisting of multiple simultaneous engines for analyzing Power, EM/IR-drop and Thermal. Our holistic approach achieves the necessary accuracy and our Macro Modeling hierarchy enables our tool to run the largest designs with lightening fast runtimes.
  • Our secondary platform is our InVar Frontier 3D Platform for true 3D thermal analysis. We scale from sub-transistor level to complex stacked-die package environments. Using physical parameters we bring a whole new level of capability for 3D thermal analysis.Invarian is the only provider of physical sign-off tools that offers concurrent analysis of various power integrity parameters as a whole. First time silicon success with the optimum design for performance and accuracy requires tools that accurately model real behavior.Why did Invarian start?
    Our founders have been working in the areas of power, voltage and thermal analysis for many years. They experienced first-hand many cases where designers got faulty silicon solely because of misleading or incomplete sign-off results. From this sprang the idea of delivering a perfectly accurate and physically correct analysis tool. The idea itself is very simple – analysis should reproduce/model physical conditions of real ICs as close as possible. Designers must have a tool that exactly models the behavior of real silicon before manufacturing. Our tool removes uncertainty, and the resulting expensive re-spin cycle, from the design process. The passion that began with our quest of building an analysis solution that reflects physical reality itself continues to resonate and drive us today.

    What is Invarian’s Roadmap?
    We are constantly updating our engines to stay ahead of the competition. One of the great things about being a new entrant in an established industry is being unbound from outmoded legacy. We have been able to build our solution from the ground up to take advantage of the latest methodologies, such as parallel processing. This has allowed us to analyze huge designs (over 150,000,000 cells) in one pass, which has historically been impossible, so our customers are very excited to finally have such powerful capability. We integrate seamlessly with the major implementation flows and SPICE engines. Enabling our customers to perform highly accurate analysis within their existing flow with a powerful GUI and ‘what-if’ capability gives them the peace of mind of knowing precisely their chip’s design behavior. Looking ahead we shall continue to listen to our customers and that is what drives our technology development and roadmap. We have some exciting announcements to make in the near future and look forward to sharing those with you.

    Will you be at Design Automation Conference this year?
    Yes, we will be in the center of the show in booth #1332 and will have suites available for private showing of our new releases; these are very exciting and will benefit any new and older generation process node designs. Please visit www.invarian.com/events.html to sign up for a demo of our solution…

Also Read:

CEO Interview: Jason Xing of ICScape Inc.

Atrenta CEO on RTL Signoff

Sanjiv Kaul is New CEO of Calypto

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