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IC/Package/Board – Power, Noise and Reliability from ANSYS (Apache DA) at DAC

IC/Package/Board – Power, Noise and Reliability from ANSYS (Apache DA) at DAC
by Daniel Payne on 04-30-2014 at 10:04 am

ANSYS acquired Apache Design Automation back in June 2011and three years later the name “Apache” is being subdued in favor of using just ANSYS. One thing that I noticed right away was a DACfocus on having actual ANSYS customers talk about their hands-on experience using the EDA tools. The following seven customers are designing for automotive, mobile, IoT and other markets:

  • Applied Micro
  • Ciena
  • LSI
  • NXP
  • Samsung
  • STMicroelectronics
  • Synapse

ANSYS setup a special web site for DAC 2014 to explain their involvement in the challenges of design across the IC, package and board levels for power, noise and reliability. You can register now to hear about either the EDA software technology, or from customers using the tools. Here are the sessions planned for ANSYS at booth #1413:

  • Totem™ – Technologies for Analog / Memory / Mixed-Signal Designs
  • Thermal Reliability for FinFET based Designs
  • PowerArtist™: RTL Design for Power Platform
  • Achieving Power Noise Reliability Sign-off for FinFET based Designs
  • Systems and Software Development Solutions for Innovative Automotive Systems
  • Simulating Automotive EMI/EMC Issues at Component, System and Wide Scale Environment Levels using ANSYS Tools
  • Designing Wireless Systems for Wearable Electronics and the Internet of Things (IoT)
  • How to Identify and Prevent ESD Failures using PathFinder™
  • What’s New in RedHawk™ 2014
  • Achieving RTL Power Efficiency with Interactive Debug and Automated Power Reduction
  • RedHawk™ -CPA: New Paradigm for Faster Chip-Package Convergence
  • IP Design Essentials for Power Noise and Reliability Sign-off
  • Methods for Achieving RTL to Gate Power Consistency
  • How to Ensure Power Thermal and Signal Integrity in 3D-IC Designs
  • How to Identify and Prevent ESD Failures using PathFinder™
  • System Power Analysis with Correlation Results for Advanced Processor Designs
  • Managing Electronic System PI, SI, EMI and Thermal Challenges using Chip-Package-System (CPS) Methodology
  • Generating Power, Noise and Reliability Aware Power Grid Prototype Early in the Design Cycle
  • Noise Coupling Analysis for Advanced Mixed-Signal Automotive ICs
  • Full DDR Bank Power and Signal Integrity Analysis with Chip-Package-System Coupling
  • Designing Smart Power-Grid with Reduced Die-Area using RedHawk
  • Silicon Correlation of RedHawk Dynamic Voltage Drop in High Power Density Wirebond SoC for Storage Application

Outside of the booth and suites there are three more places that you’ll find ANSYS participating in at DAC:

  • Automotive village, Booth #603 – system tools to help meet performance, reliability and safety requirements
  • ARM Connected Community Pavilion, Booth #2001 – low-power design challenges
  • TSMC Open Innovation Partner Theatre, Booth #1801 – learn which ANSYS tools are TSMC-certified for 16nm FiNFET, plus 3D-IC

Finally, there are three additional topics that you can learn about:

  • Managing Multi-scale, Multi-physics Challenges in the New Generation of Automotive Systems
  • ANSYS customers on power noise and reliability analysis
  • Total Battery Simulation: Multiphysics, Multiscale Simulation of a Complete Li-Ion Battery Pack and Sub-systems

ANSYS is involved at DAC in a big way, so pick your specialty and get registered early to ensure your spot.

lang: en_US

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