WP_Term Object
    [term_id] => 34
    [name] => Ansys, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 238
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 238
    [category_description] => 
    [cat_name] => Ansys, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157

Executive Interview: Vic Kulkarni of ANSYS

Executive Interview: Vic Kulkarni of ANSYS
by Daniel Nenni on 11-07-2016 at 7:00 am

 Vic Kulkarni ANSYSHaving known Vic for many years, it is always great to spend time with him and catch up on what is happening inside the semiconductor ecosystem. As Senior Vice President and General Manager, RTL Power Business, at ANSYS in Silicon Valley, Vic spends a lot of time in the field with customers, partners, and at industry events so he has intimate knowledge of some of the changes we are experiencing, absolutely.

Prior to merging with Apache in 2009 and subsequently with ANSYS, Vic was a co-founder, President and CEO of Sequence Design. In addition to driving product and business growth within the ANSYS Semiconductor Business Unit with the senior leadership team, Vic is also evangelizing the emerging IoT opportunity along with other business units, connecting the dotsfrom chip-package-system software solutions with ANSYS multi-physics simulation tools targeted at various IoT vertical segments.

Tell us about ANSYS
We are a leading provider (Nasdaq: ANSS) of simulation products headquartered in Canonsburg, PA. The Company has been laser-focused on providing multi-physics and multi-domain simulation software to enable the product design for over 40 years! Multi-physics refers to an environment where products are subject to multiple physical forces such as thermal effects, structural integrity, electro-magnetics radiation and so on. Multi-domain typically refers to chip, package and system power domains in electronics, simulation of antenna radiation pattern, fluid dynamics to complete electro-mechanical systems. We have over 45,000 customers worldwide. ANSYS acquired Apache Design in 2011 and the Semiconductor BU of ANSYS was born.

Early this year ANSYS formally launched the IoT initiative to provide solutions for several vertical segments, ranging from Wearables, Healthcare, Automotive, Industrial, Defense to Smart & Connected Cities.

What are the key focus areas for ANSYS?
IoT is clearly an exciting business opportunity for the worldwide industry. Recently SoftBank CEO Masayoshi Son-san made a seminal statement in his keynote during the ARM TechCon Conference when he compared the emerging IoT explosion to the Cambrian explosion! He stated that chip sensing capabilities are evolving rapidly and will exceed the collective human intelligence in next few years akin to what happened to senses of intelligent animal species during the Cambrian explosion!

At ANSYS we see these rapidly growing trends especially with the Industry 4.0 applications, autonomous vehicles and advanced mobile segments. Increasingly, our customers have started to address critical challenges related to communication system design, sensor design and product reliability to out-innovate the competition. In this incredibly fast-paced environment, virtual prototyping using simulation software is an important strategic vehicle for creating a meaningful competitive advantage by getting the newest product model or next-generation features into customers’ hands as fast as possible.

Explain how ANSYS enables customers in this revolution.
This “revolution” is happening due to a confluence of several technological advances that have happened in the past decade or so, and simultaneously too.

The first one is Miniaturization – More and more electronics are being packed into smaller and smaller space, providing unprecedented processing and computing capability. The first cell phone weighed 2 pounds. In comparison, the newest generation of mobile phone weighs only about 4.6 – 4.8 ounces, and it enables you to do lot more than just talk! This type of miniaturization is enabled by smaller chips and electronic components. Now people talk about the trend towards “More Than Moore”. It refers to the fact that chips continue to gobble up more and more of the circuitry on a PCB. This kind of integration is enabling miniaturization at the larger scale, enabling planes, cars, drones, and virtual reality systems to get more sophisticated.

As an example for a connected car the performance and ADAS model must be tested in a simulated model of roads, buildings and pedestrians under diverse driving scenarios. Whether designing planes, cars or smartphones, engineers typically need to optimize IoT products for size, weight, power and cooling — a set of design requirements popularly known as “SWAP-C.” Engineers must manage all these components in a constrained space, while optimizing performance. This means relying on simulation to make design trade-offs quickly and cost-efficiently.

ANSYS provides a complete platform for engineering simulation, product designers can identify and address any functional flaws, such as impractical power demands at the chip, package and board level or faulty antenna design, as quickly as possible — and as early as possible in the design cycle, when mistakes are less costly to address.

According to an independent study of over 600 companies done by the Aberdeen Group clearly states that simulation is a key enabler in product design, reducing development time by 9X, reducing the overall product cost by 4X, with over 85% more likely to decrease the warranty costs and new product introductions with a success rate of over 65%!

How does Semiconductor Business Unit (SCBU) fit in the overall ANSYS Corporate strategy?
Apache Design (now called Semiconductor Business Unit) has been one of the important strategic acquisitions that ANSYS has made over the years to enable simulation of a complete electronic system design— from IP, Soc level RTL power analysis and power reduction, power integrity sign-off including dynamic voltage drop, electro-migration, on-chip ESD, and co-simulation of package, board and system level thermal and power effects in the context of chip-level dynamic voltage drop.

Designers are now able to analyze dynamic voltage drop of a complete SoC and evaluate its impact on the downstream electro-magnetic radiation signature analysis and system level thermal analysis. This is rather critical for designers to understand the overall system-level behavior in various vertical applications such as autonomous vehicles, health-care to advanced mobile devices.

What keeps you awake at night?
We have 290+ employees in our SCBU singularly focused on addressing the challenges posed by the most energy-efficient IP, SoC and electronic system designs.

There are 3 main areas which keep us awake at night:

  • N7 technology challenges
  • A comprehensive Chip-Package-System (CPS) simulation solution
  • Big Data for EDA with elastic compute driven architecture for next-generation SoC design challenges

We have seen complexity of designs exploding to Bn+ logic instances with 1,000+ I/Os, technology nodes going from 40 nm to 7nm feature sizes in just a few years. Along with the technology process node, innovative packaging techniques have kept up the pace as well… from a 2.5/3D package configuration to technologies such as InFO-WLP improve power, performance and reduce form factor.

The stakes are obviously very high when as much as $250+million investment and 500+ person-years (Ref: Gartner) are needed to bring a 7nm SoC to market.

As an example, meeting a 15 percent dynamic voltage drop limit in a 7-nm design running at 500mV is extremely challenging since the design trade-off choices that affect die-size, schedule and performance must be made to achieve the desirable outcome. On-chip variation, electro-migration (EM) and ESD sign-off considerations require careful modeling of advanced extraction and foundry rules both in an N7 chip and its InFO-WLP package. Accuracy convergence methodology must be followed rigorously from register-transfer level (RTL) power budgeting, estimation and regression to the final sign-off before committing to silicon.

At our Business Unit currently we are tracking 8 customers who are designing 7-nm SoCs. Complexity of these chips can range from 2- 4+ billion logical instances, with the number of physical geometries reaching 40 billion and parasitics reaching 400+ billion. One can now say we are reaching the “Big Data” problem!

The traditional architecture of EDA tools must be transformed. Why?
Conventionally EDA databases have always remained in silos and are structured (SQL – structured Query Language). They all use the exact same traditional monolithic database and data model systems. e.g. netlist, layout, logic, timing, RC, timing and so on. So it has been very challenging for engineers to readily explore design alternatives for an optimal solution where one physical effect can have serious impact on the other, e.g. voltage on timing. Our purpose-built SeaScape architecture is based on the principles of Big data elastic-compute principles to address these challenges since it enables a designer to run hundreds of what-if experiments in the time it used to take to build a single prototype, and create highly optimized designs.

To do this you will need to move away from the traditional silo-based design flow to a chip-package-board co-simulation workflow and methodology.

By leveraging chip-package-system flows and methodologies to target 7-nm technologies, one can achieve faster design convergence along with considerable business advantages. You can additionally profit from the reduced power consumption, higher speed and density improvements available from the 7-nm process node. Such simulation flows and solutions have to meet two broad requirements to make a meaningful impact: they must provide multi-physics sign-off accuracy and coverage, and enable accelerated design closure and optimization.

In addition, signal integrity analyses need to expand beyond traditional “SI” or cross-talk focus to include coupling of power rail and signal noise to predict jitter and noise coupling both inside and outside the chip to meet stringent DDR, SerDes data rate specifications.

Also Read:

CEO Interview: Taher Madraswala of Open-Silicon

CEO Interview: Simon Butler of Methodics

CEO Interview: Charlie Janac of Arteris


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