When Charlie Janac talks, people listen, absolutely. Charlie’s 30 year career spans EDA, IP, semiconductor equipment, nano-technology, and venture capital. For the last 11 years he has been CEO of interconnect IP provider Arteris who invented the industry’s first commercial network on chip (NoC) SoC interconnect IP solutions and continues to lead the industry. In 2013 Charlie engineered a landmark acquisition deal with Qualcomm while retaining the right to license, support, and maintain the existing Arterisproduct lines.
What are some of the latest developments at Arteris?
I am happy to report that in 2016 Arteris will be at almost at the same revenue level and engineer staffing level as we were in 2012, the year prior to our technology asset transaction with Qualcomm. We have shipped a major new product every year for the past three years – Interconnect resilience for mission critical SoCs in 2014, automated interconnect timing closure in 2015 and our Ncore cache coherent interconnect in 2016. We are confident these technology deliverables have come at a more rapid rate then our competition. Furthermore, these new interconnect products have been designed into some of the leading SoCs for mobility, automotive, networking, SSD and consumer applications. At the same time, our FlexNoC non-coherent interconnect continues as the leading market share interconnect IP in its category with two new product releases this year alone. The best indication of new product technology features and quality is customer adoption. We have added nearly 30 new customers since 2013 as well as received major reorders from our existing licensees. Arteris continues to deliver quality interconnect IP products out of engineering and it continues to get them broadly adopted by semiconductor and system OEM companies.
What is the importance of interconnect IPs? Is that importance growing?
SoCs are now assembled out of internal and commercial IP blocks and one of the important differentiators is how that IP is assembled. While the majority of the IP blocks are proven, they have relatively fixed functionality – it is the interconnect IP that changes many times during the course of a project and almost always changes between projects. Therefore, it is mission critical for SoC implementation companies to have the most efficient, highest performance, and cost effective interconnect IP in their designs. The 10/7nm generation of designs will also lead to yet another level of increasing interconnect complexity and so will the move to 2.5 and 3D silicon.
The importance of SoC interconnect technology is growing with each generation of new system-on- chip devices. The network-on-chip (NoC) type interconnect that we pioneered was widely adopted in the 40nm generations of SoCs between 2008 and 2009. The 16/14nm FinFET-type SoCs of today represent another inflection point in terms of architectural complexity. IoT chips are requiring a step function increase in battery life which in turn is driving power management complexity. This is yet another important driver for our interconnect IP.
Do you see a shift in IP market segments?
We are absolutely seeing shifts in IP market segments. Back in 2013 we had 20 out of 23 mobility SoC makers license our FlexNoC interconnect IPs. Today it is seven out of 10. The mobility market did not shrink but it became much more consolidated and it will consolidate still further. The growth of this market is still attractive but it has slowed significantly.
Conversely, Arteris had one automotive SoC licensee in 2012 while today it is nine. The automotive SoC market is being driven by two developments: (1) much greater use of electronics, driven by self-driving and over-the-air updating capabilities, and (2) the replacement of multiple microcontrollers by fewer and larger SoC-type semiconductors. The car is becoming one of the most useful IoT devices. Mobility is still the larger SoC market but automotive is now and will continue to be the fastest growing.
Another set of IP market shifts is related to geography. While semiconductor growth has slowed in many parts of the world, growth in China is accelerating. This is partially driven by government investment and partially driven by increasing domestic consumption of electronic devices. For every company that has merged with another in the semiconductor world, there is another reasonably sized company starting in China. As a result, on the global scale, the number of SoC projects should remain relatively stable while volumes continue to increase.
Is the ARM acquisition by Softbank good or bad for other IP companies?
It may be to too early to tell what impact Softbank’s ARM acquisition will have, but I think it will be relatively neutral compared to ARM’s acquisition by either a semiconductor or systems company. That is a good development. However, Softbank paid $32 billion for a company that has $1.6 billion in revenue, so therefore, it’s safe to assume some things will change as a result. We have to watch how things evolve. My hope is that the ARM architecture continues to be an open ecosystem as it has been in the past, because that has fueled innovation and growth.
What is the significance of the self-driving car for companies like Arteris?
Arteris is heavily focused on needs of our automotive customers for both functional safety features and ISO26262 compliance and documentation. In my opinion, the automation technology used in assisted driving vehicles will ultimately have even greater impact on society than the smart phone. The impact will not only be seen in cars but also trucks, drones, public transportation vehicles and vehicle types we cannot even fathom yet. The self-driving car is an immensely complex system and so the industry has to evolve over time. The automated highway driving scenario is reasonably close to being solved but the city driving scenario represents another level of complexity. We will see increased investments in the electronics that will underpin the infrastructure to support this evolution in ways that we cannot completely predict today. Ultimately, there may be some segregation of automated and human-controlled vehicle traffic.
The automation-assisted vehicle are mission critical systems that must work as well as we can possibly make them. Therefore, companies such as Arteris have to deliver functionally safe IP that supports the safety objectives of the transportation industry. One of our technology directions is to deliver resilient interconnect IP that is tolerant of errors due to environmental radiation and manufacturing flaws. This technology has to be backed up by documentation and analysis for standards compliance, and working silicon must be proven in the field. All of this requires a large investment by the semiconductor IP company, so you have to see significant customer adoption to be able to profitably sustain these kinds of developments.
There are many opportunities for innovation in this segment. Today, we are delivering a resilient, fault-reporting interconnect, but ultimately, we need to get to a truly fault tolerant interconnect..
What are some of the technology challenges posed by FinFET technologies?
One of issues that has been increasingly troublesome for customers is timing closure. It has become so complex that it is putting delivery schedules of major SoCs at risk. When you cannot go across the entire chip from initiator IP to a target IP in one clock cycle, you have to insert repeaters or pipelines. Each pipeline can be made up of several choices of register configurations. And a complex SoC can have 6,000 factorial (2.68 x 102068 ) pipeline choices or more. This level of complexity exceeds the human level of optimization so the process must become more automated. The benefits of automation of timing closure includes saving months of effort that can impact SoC delivery schedules and a timing closure scheme that is not over engineered in terms of area, power and latency, resulting in lower R&D and SoC unit costs. Automated timing closure is enabled by NoC type interconnects because it separates the interconnect IP from other IPs in the design, allowing a separate interconnect timing closure process. From everything we see, the days of manually closing timing for complex SoCs are quickly coming to an end.