Webinar: Connecting Chiplets Isn’t Enough – Solving the Data Movement Challenge in Multi-Die Systems

Webinar: Connecting Chiplets Isn’t Enough – Solving the Data Movement Challenge in Multi-Die Systems
by Admin on 10-27-2026 at 11:23 pm

Thursday, November 5, 2026

11:00am PST | 2:00pm EST | 20:00 CET

As SoCs evolve into multi-die systems, getting data across a die-to-die interface is only part of the challenge. Architects must also preserve traffic behavior, bandwidth efficiency and quality of service as communication moves across physical chip boundaries.

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Webinar: Your Chip Works. Prove It Is Secure.

Webinar: Your Chip Works. Prove It Is Secure.
by Admin on 10-27-2026 at 11:13 pm

Tuesday, November 10, 2026

8:00am PST | 11:00am EST | 17:00 CET

Functional verification establishes that a chip performs its intended functions. Hardware security assurance, however, addresses a different set of questions: Can sensitive information reach unauthorized destinations? Can protected state be modified unexpectedly?

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Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks

Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks
by Bernard Murphy on 10-21-2026 at 6:00 am

MultiDie FlexGen

Last year I wrote about Arteris’ introduction of multi-die support for coherent NoCs. This is a very big deal because hyperscalers and OEMs are now building large systems that depend on multi-chiplet architectures and require efficient traffic management between chiplets, in one case as many as 12 compute, fabric/cache and … Read More


Security by Design: Arteris Expands Its Partnership with Arm

Security by Design: Arteris Expands Its Partnership with Arm
by Daniel Nenni on 07-28-2026 at 6:00 am

Arm Arteris Cycuity Announcement 071026

Arteris has expanded its partnership with Arm to deploy Cycuity Radix hardware security assurance technology across additional next-generation Arm central processing unit (CPU) programs. The expansion follows five years of collaboration and successful use of Cycuity Radix on select Arm CPU designs, and it moves hardware… Read More


Arteris at DAC 2026 Connecting Innovation for Silicon Success

Arteris at DAC 2026 Connecting Innovation for Silicon Success
by Daniel Nenni on 07-15-2026 at 6:00 am

Arteris Company banner

The semiconductor industry has entered a new era as AI workloads, chiplets, heterogeneous computing, software-defined vehicles, and intelligent edge devices are transforming how chips are designed.

Silicon success is no longer determined by transistor counts alone, but by how efficiently data moves across increasingly… Read More


Podcast EP350: The Growing Threat of Hardware Security Breaches and What to do About it with Dr. Andreas Kuehlmann

Podcast EP350: The Growing Threat of Hardware Security Breaches and What to do About it with Dr. Andreas Kuehlmann
by Daniel Nenni on 06-12-2026 at 10:00 am

Daniel is joined by Dr. Andreas Kuehlmann, General Manager of Security Solutions at Arteris. He has over 35 years of experience in semiconductor design, software, and cybersecurity, including roles at IBM Research, UC Berkeley, Cadence, and Synopsys. Previously, he was CEO of Cycuity, which was acquired by Arteris.

Dan explores… Read More


How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler

How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler
by Daniel Nenni on 06-12-2026 at 6:00 am

Kurt Shuler

Arteris is one of the most impressive companies SemiWiki has worked with over the last fifteen years. We have collaborated on one hundred and seventy-three articles/podcasts that have garnered more than two million views/listens. The success of Arteris can be easily tracked to the executive team and Kurt Shuler was the executive… Read More


Connecting the Dots: Why RISC-V System Design Is Entering a New Era

Connecting the Dots: Why RISC-V System Design Is Entering a New Era
by Kalar Rajendiran on 05-04-2026 at 10:00 am

Andes x Arteris Pre Verified and Silicon Proven SoC Integration

At the recent RISC-V Now event hosted by Andes, the discussion underscored the fact that RISC-V is no longer just about instruction set architecture advantages or customizable cores. The real focus has moved up the stack to system-level design. This is where connectivity, integration, and security define whether an innovation… Read More


SemiWiki Acquires IPnest!

SemiWiki Acquires IPnest!
by Daniel Nenni on 04-24-2026 at 8:00 am

AI IP Image

After more than 15 years of collaboration with Dr. Eric Esteve and IPnest, SemiWiki has acquired the famed IP reports with Eric Esteve staying on through 2026 to ease the transition. Not only will SemiWiki provide the industry standard Interface IP and Design IP reports, SemiWiki will be expanding the depth and breadth of the coverage.… Read More


NoC Matters: Designing the Backbone of Next-Gen AI SoCs

NoC Matters: Designing the Backbone of Next-Gen AI SoCs
by Daniel Nenni on 04-13-2026 at 10:00 am

Arteris NoC Hardware

Modern SoC design for artificial intelligence workloads has fundamentally shifted the role of the network-on-chip (NoC) from a simple connectivity fabric to a primary architectural determinant of system performance, power, and scalability. As compute density increases and heterogeneous accelerators proliferate, data… Read More