Laboratoire d’électronique des technologies de l’information (LETI) is a French research center, affiliate to the CEA (Commisariat a l’Energie Atomique). Since LETI creation in 1967, this affiliation has two consequences, the money was flowing from the deep pocket of the atomic industry to sustain advanced research at LETI and the secrecy was part of the research center DNA. The first point was true until recently, when the French state decided that the LETI operations should be balanced with external funding coming from the industry for more than 40% of the budget. As a research center, LETI still highly valorize confidentiality, but can now speak more openly to promote some of the research.
This decision has generated a bunch of opportunities for LETI to find industry partners, from small or medium-sized enterprises (SMEs) benefiting from LETI’s engineer expertize to develop a product, up to the large semiconductor companies like Intel, Qualcomm, ST-Microelectronics or GlobalFoundries. Marie-Noelle Semeria is LETI CEO since October 2014 and she has a strong vision about the evolution of the electronic industry and about how LETI can play an active role in this revolution. I had the opportunity to speak several times with MN Semeria during interviews or open discussions, and I really appreciate her scientist background. She knows about the technology and she has a global view about electronic, even if her main tasks are to manage a 1300 researcher’s team (1900 including assignees) and to find new markets for LETI.
According with MN Semeria, several technologies developed by LETI to support emerging electronic systems are currently licensed by top semiconductor companies, like CoolCube (3D chips integration), High Performance Computing (HPC) disruptive architectures or Silicon on Insulator (FD-SOI), not mentioning nanotechnologies for biology and healthcare. If you talk with a project manager involved in advanced chip design, you will probably discuss about the challenges linked with moving from 14nm to 10nm, the always increasing development cost you need to pay to follow Moore’s law and so on. Talking with LETI CEO opens new doors as the research center is developing some technologies that will complement Moore’s law like FD-SOI, and also certain being disruptive enough to permit the creation of post-Moore silicon based industry.
FD-SOI is one of the hot topics these days, it was the focus of this interview and MN Semeria had a lot to share with Semiwiki about the technology.
FD-SOI: Power consumption, Performance and Cost
Better power consumption is one of clear benefit bring by building a Field Effect Transistor (FET) on an insulated substrate, by opposition with a bulk. In fact, a SOI wafer is a regular silicon wafer where a thin silicon oxide has been deposited. Because they are raised on this oxide box (see picture) and not directly on the silicon substrate, the drain or source parasitic capacitance is almost nulled. If you remember the formula (P=aCV[SUP]2[/SUP]) you know why the parasitic power consumption linked with source/drain to substrate capacitance has disappeared. Many others parasitic capacitances between the metal lanes and the substrate will also significantly decrease, if not disappear. Transferring a bit of information in an IC consist in charging a metal wire (which can be as long as the IC half perimeter) and the gate of the MOSFET you are addressing to, that’s why decreasing these parasitic capacitances has a real effect on the power consumption. Taking the 10nm FinFET as a reference, the work made in LETI labs says that you can reduce the power consumption by 40% for a 12FDX device.
In term of pure performance MN Semeria agrees that FinFET will always lead the pack (at similar geometry) and says that for applications like data center or high-end mobile application processor, chipmakers will continue to stick with FinFET technologies. She is not trying to put the two technologies in direct opposition, but she says that both are complementary. It could make sense to design low-end mobile application processors on FD-SOI. When you need to boost a FD-SOI device performance, you can use a kind of “overdrive”, the forward bias. In fact, as you can access the (deep) silicon substrate (see BP on the picture), you can apply a forward voltage to the body, or forward body bias (FBB) to increase the raw performance of the FET device. This is like benefiting from high performance, but just on-demand, and low-power the rest of the time. According with MN Semeria, you can get identical performance with 12FDX and 10nm FinFET.
If you consider the technology evolution when strictly following Moore’s law (28nm and 20nm planar, 16nm, 10nm and 7nm FinFET), you quickly realize that each time you go down by one node to benefit for better performance and lower power consumption, you pay the bill in term of development cost or non-recurring engineering cost (NRE). This is true if we look at the design cost, and this is also true if we take into account the mask and wafer processing costs. These extra processing costs are linked with double, triple or even quadruple patterning. According with MN Semeria, processing a 12FDX wafer only require double patterning, allowing 40% cost savings compared with 10nm FinFET. If we expect the semiconductor industry to keep innovating, and see many chip design starts in the future, some of these will have to target technologies offering lower development cost and still decent performances.
FD-SOI: Ecosystem, Roadmap and the 80 Tape-out
If you remember, the origin of SOI technology was linked with the atomic industry, and the reason is that SOI devices have a much better immunity to radiation. This radiation immunity is a benefit for RF and memory designs at chip level and for the automotive industry at system level. When designing for Internet of Thing (IoT) or for wireless mobile, the long term trend will be to integrate RF into a super-application processor. Trying to integrate RF into a FinFET chip seems to be extremely difficult, it’s due to the quantum architecture (one Fin, two Fin, etc.) not allowing a smooth analog design as with planar.
The automotiveindustry has become very dynamic and we see numerous advanced SoC design start to support the emerging automotive applications (ADAS…). But automotive is also an industry where you have to design in a harsh environment (temperature, vibrations, dust, etc.) and FD-SOI appears to be well suited. Automotive is also very different from the mobile industry for example, as the design cycle and product lifetime are very long. In other words, the automotive industry needs to rely on a solid roadmap.
We have seen in a recent article that GlobalFoundries has announced the availability of the 12 FDX technology for tape out in 2019, designs are on-going on 22FDX, and Samsung is thinking about 20FDSOI and count TO on 28FDSOI. LETI is a research center, as such they have to explore the next FDSOI steps and MN Semeria says that they did so for 10nm and 7nm. LETI has test results on silicon at 10nm and they have checked 7nm feasibility. In fact, you have to remember that when the FDSOI technology was licensed by GlobalFoundries, LETI has sent a 10 engineer team to Dresden to support, first 22FDX, then 12FDX, development. This team is complemented by the Grenoble based characterization lab in LETI campus. To summarize, the FDSOI technology roadmap is solid: 28nm (ST-Microelectronics and Samsung), 22nm (GloFo and Samsung), 12nm (GloFo with LETI), 7nm (LETI development). For more precise information about the FDSOI technology nodes, see this blog from Scotten Jones.
I was surprised when MN Semeria mentioned that 80 chips will be tape-out on FD-SOI, but after checking the number, it’s made of 50 customers already engaged with GloballFoundries (as announced by Alain Mutricy at SOI Shanghai this September), 12 tape-out announced by Samsung for 2016 and the rest being split between ST-Microelectronics and chips in design at Samsung.
Last but not least, the ecosystem created around FDSOI technology is real. LETI has designed the foundation IP to support GloballFoundries customers on 22FDX (we can guess that Samsung’s customers on 28nm have used the IP developed by ST-Microelectronics). LETI is also supporting GlobalFoundries FDXcelerator Partner Agreement, aimed at offering a complete ecosystem of IP and services to customers to design on FDSOI. If you search for more complex IP, like CPU cores, you should know that ARM supports both 28nm and 22nm and for interface (USB, PCI Express, etc.), these IP are supported by many vendors (Synopsys, Cadence, Verisilicon, Sankalp…).
I expect to tell you more about these technologies, in some cases disruptive, that we will have to consider in the future, if we want the semiconductor industry to stay the place where innovation takes place. Moore’s law is not dead, it will continue through FinFET technology development, but this technology will have to be complemented with other technology options (FD-SOI…), new chip architectures (HPC…), new packaging (3D, TSV, 2.5D…) and more (than Moore!).
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