This is the second in series of interviews we will do with executives inside the fabless semiconductor ecosystem. Geoff Tate was the founding CEO of Rambus and is now CEO and co-founder of Flex Logix (embedded FPGA). This one should be of great interest due to the recent $16.7B acquisition of Altera by Intel. We all now know the importance of having programmable logic inside data center chips but what about networking, automotive, AI, and IoT chips? And do you really have to pay $16.7B to have it?
What does Flex Logix do?
We provide embedded FPGA as hard IP cores along with the software to program them. Our embedded FPGA has density similar to a Xilinx FPGA, with 90%+ utilization, using a minimum-metal stack in each node (4-6 metal routing layers), with no extra masks or process waivers.
Today, we offer embedded FPGA in TSMC 28nm and 40nm nodes, proven in silicon; and we will shortly make embedded FPGA available in TSMC 16nm. Our software has been working for more than a year and we have customers in design today.
Our customers are chip companies (or system companies big enough to design their own chips) who integrate our embedded FPGA into their SoC/MCU/IOT chips to be able to reconfigure critical RTL at any time. It can cost a company multiple millions of dollars and add 3-6 months to the schedule if they have to change the RTL at any time during the design process. With embedded FPGA, we can eliminate those costly and time-consuming setbacks. And with embedded FPGA, critical RTL can be updated in the system extending the effective lives of chips and systems both, increasing ROI.
What can an embedded FPGA do that an FPGA chip cannot?
There are numerous new architectures and applications we are enabling that were not previously possible.
One example is fast control logic. A block of ~1K LUTs worth of reconfigurable logic in 16nm can have 512 control inputs with reconfigurable RTL that generates ~100 control outputs with a clock rate of ~1GHz. Imagine trying to do this with an FPGA chip? The SoC would need 512 signals going off-chip to the FPGA with the associated pins for power/ground at ~1GHz signaling with another ~100 pins coming back. The cost to do this would be enormous in packaging and the routing would kill the latency and frequency.
IO width and clock frequency is the number one reason embedded FPGA can do things external FPGA cannot. This is analogous to on-chip SRAM which can easily have very wide 64/128/256/512 bit buses with high clock rates whereas connecting an external SRAM chip to an SoC means narrower buses and lower frequencies due to package costs, PCB signaling speed difficulties, etc.
Another example is in a 40nm microcontroller where we’ve seen a small block of reconfigurable RTL with DSP acceleration execute certain DSP functions with 2x-5x less energy than an ARM core, even before considering the ARM core memory access energy. The EFLX embedded FPGA is faster than the ARM core, so an EFLX array can monitor and process certain critical signals at a significant improvement in battery life, only waking up the processor core when needed. This benefit can be realized with 300-400 LUTs with integrated MACs operating at 0.9V. There are few FPGA chips anymore with this little capacity and they operate at higher voltages and do not have integrated MACs.
How will chip companies benefit from embedded FPGA? Systems companies?
Many microcontroller families at 90nm have dozens or even hundreds of SKUs to handle a wide range of end user requirements, which really are just small variations of a master design. A typical example would be different serial protocol needs (SPI vs UART vs I2C vs…). Now that leading-edge microcontrollers are just beginning to migrate to 40nm where mask costs are ~$1M, embedded FPGA provides a zero-mask-cost solution to meet different customers’ needs. This enables customers to quickly respond with solutions to new requests without having to re-tape out and validate a new chip.
Initial uses in microcontrollers may be invisible to the systems customer. However, as microcontroller companies become comfortable with embedded FPGA, the next logical step is to enable systems customers to program reconfigurable RTL blocks both in the I/O subsystem and on the main processor bus. This will enable customers to implement acceleration blocks to augment their specific application.
In the data center, there is apparently a desire to build systems and never touch the hardware for the life of the data center. This is challenging to do considering the changing standards for protocols, packets, etc.. Reconfigurable RTL solves that issue because it can be updated at anytime to keep up with new standards, even custom versions only used by one customer.
In base stations, reconfigurable RTL enables reconfigurable Digital Front End DSP processing to handle the availability of new frequencies and other customer requests.
In NVM memory, there are numerous new technologies emerging. With reconfigurable RTL, the memory interfaces can be made flexible enough to adapt post-design to handle the variations in timing sequences and error correction algorithms that rapidly evolving new NVM technologies (MRAM, ReRAM, Xpoint, etc) require.
The overall benefit to everyone involved is that chips and systems have longer, more productive lives and can satisfy a broader range of customers and applications. This reduces inventory and production costs, and increasing sales and ROI.
What applications are the early adopters of embedded FPGA?
We see strong interest in embedded FPGA in a very wide range of technologies from <$1 microcontrollers/IoT to very high-end networking chips.
The early adopters are in microcontrollers, signal processing, networking, communications, and defense applications where the need is very clear and the value is very high. Even with these applications, customers insist on seeing our IP proven in silicon and typically do very extensive due diligence of architecture, software and physical design to be sure we are ready, which we are, before proceeding.
How big can the market for embedded FPGA be over time?
Almost every customer we have talked to says, “this can be a very useful technology.”
Many customers are still figuring out how best to use our technology because no architectures have ever existed with reconfigurable RTL that are fast and dense. To help them, we recently hired a Director of Solutions Architecture who joined us from Intel where he was a Lead Systems Architect on numerous volume Desktop CPUs. Before that, he was an architect for numerous Sun servers. He has already done an extensive energy analysis which is available on our website and shows we save energy for DSP applications in 40nm. We are now actively hiring to build his team up to meet customer demand for architecture assistance.
We’ve noticed that many customers want to wait until others come to market. I saw this at Rambus where I was the founding CEO. At Rambus, the success of Nintendo’s N64 triggered an avalanche of adoption from numerous customers, including Intel, who had been carefully evaluating and preparing till they saw the first million-unit-plus application. I believe this will also happen with embedded FPGA. In time, I personally think embedded FPGA can become a very pervasive technology. This is NOT a niche technology.
Do you compete with Xilinx and Altera? Why don’t they provide embedded FPGAs if there is a need?
We don’t compete at all. My co-founder Cheng Wang talked with several FPGA companies before we started Flex Logix. Then after the company was founded, we had several more discussions when Cheng’s paper on his patented interconnect technology came out. These discussions were initiated because of their interest in understanding Cheng’s work. We learned two things from these discussions with people at senior levels:
First, traditional FPGA companies are all heavily invested in complex and widely used software. This makes changing their hardware interconnect architecture very unattractive, even if it is better. This situation is similar to CISC vs RISC back in the 90s.
Second, they had been asked periodically by companies to provide embedded FPGA, but they were uninterested in doing so. They have an attractive business building chips for which they don’t have enough engineers. The companies weren’t willing to pay very much, compared to the opportunity cost for the resources required; and the business model of providing IP is very, very different from that of selling chips.
As a result, the FPGA chip companies are like Intel and AMD who never competed with ARM in the embedded processor IP space. The chips are used in different ways in different applications by different customers than is the embedded IP.
What are your major challenges?
At this point, the major challenges are primarily behind us. We had to show that our technology worked, and we now have working silicon in two process nodes. We have customers designing complex chips who have successfully integrated our embedded FPGA and also using our software in the process.
We have customers adopting our technology, with customers in design now, and we are actively in negotiations and technical due diligence with many more.
We also had to show we could fund a semiconductor IP business. We stayed lean and focused on building silicon and software on a small seed round, then raised a Series A of $7M+ when we proved silicon and got customers designing chips with our technology.
Today, our major challenge is meeting our existing customer commitments and hiring and training staff fast enough to keep up with rapidly growing demand from new customers. For a while now we have been in constant recruiting mode and I expect we will stay there. We are constantly talking to a wide number of interested applicants and are always looking for the most qualified and motivated new hires to join our team as we need them. In fact, we are hiring “ahead of the curve” since we have to train people on a new technology and methodology and we want to make sure we have capacity to meet customer needs.
While any new technology, particularly one that has never existed before, is challenging, if you visit our offices, you’ll see us working hard and having a lot of fun working together as a team.
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