5G, Hyperscaling and the Resurgence of Consumer Silicon

5G, Hyperscaling and the Resurgence of Consumer Silicon
by Ramsay Allen on 10-04-2020 at 6:00 am

TSMC 5G OIP 2020

At the recent TSMC OIP Ecosystem Forum and Technology virtual events, TSMC re-affirmed their previous prediction that 5G is going to be a multi-year silicon mega-trend with the biggest drivers being the ramp up of 5G handsets, supporting infrastructure and the continued growth of high performance computing (HPC).

We all want… Read More


A “Super” Technology Mid-life Kicker for Intel

A “Super” Technology Mid-life Kicker for Intel
by Tom Dillinger on 08-17-2020 at 10:00 am

TigerLake WillowCove

Summary
At the recent Intel Architecture Day 2020 symposium, a number of technology enhancements to the Intel 10nm process node were introduced.  The cumulative effect of these enhancements would provide designs with a performance boost (at iso-power) approaching 20% – a significant intra-node enhancement, to be sure.  The… Read More


Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions

Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions
by Admin on 08-06-2020 at 10:00 am

Explosive data growth has led to significant power bottlenecks from the data center to the edge. Enter the Renaissance of Computing, featuring purpose-built accelerators that solve these problems, significantly speeding up AI applications such as training and model inferencing in the cloud and at the edge. Utilizing these
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Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions

Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions
by Daniel Nenni on 07-29-2020 at 10:00 am

Globalfoundries AI Webinar Hiren Majmudar

I had the pleasure of spending time with Hiren Majmudar in preparation for the upcoming AI Accelerators webinar. As far as webinars go this will be one of the better ones we have done. Hiren has deep experience in both semiconductors and EDA during his lengthy career at Intel and now with a pure play foundry. He is intelligent, personable,… Read More


Staying on the Right Side in Worst Case Conditions – Performance (Part 2)

Staying on the Right Side in Worst Case Conditions – Performance (Part 2)
by Tim Penhale-Jones on 07-02-2020 at 10:00 am

Moortec Part 2 Talking Sense

In this, the second part of a two-part series we delve further into defining worst case, this time focusing specifically on device performance.

In the last blog we talked about the steady increase in power density per unit silicon area and how worst case is definitely getting worse. We discussed how in each new FinFET node the dynamic… Read More


Contact over Active Gate Process Requirements for 5G

Contact over Active Gate Process Requirements for 5G
by Tom Dillinger on 07-01-2020 at 6:00 am

frequency 5G

Summary
A recent process enhancement in advanced nodes is to support the fabrication of contacts directly on the active gate area of a device.  At the recent VLSI 2020 Symposium, the critical advantages of this capability were highlighted, specifically in the context of the behavior of RF CMOS devices needed for 5G designs.

IntroductionRead More


Contact Resistance: The Silent Device Scaling Barrier

Contact Resistance: The Silent Device Scaling Barrier
by Fred Chen on 05-24-2020 at 6:00 am

Contact Resistance The Silent Device Scaling Barrier

Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation.

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MOSFET Gate Length Scaling Limit at Reduced Threshold Voltages

MOSFET Gate Length Scaling Limit at Reduced Threshold Voltages
by Fred Chen on 05-10-2020 at 6:00 am

MOSFET Gate Length Scaling Limit at Reduced Threshold Voltages

As transistor dimensions shrink to follow Moore’s Law, the functionality of the gate used to switch on or off the current is actually being degraded by the short channel effect (SCE) [1-5]. Moreover, the simultaneous reduction of voltage aggravates the degradation, as will be discussed below.

A Practical Lower Limit ofRead More


Talking Sense With Moortec…Are You Listening?!

Talking Sense With Moortec…Are You Listening?!
by Tim Penhale-Jones on 05-04-2020 at 10:00 am

Ear no evil

It almost doesn’t matter what your job may be, whether in the public sector or a private company, or how technical or how dangerous, many of life’s adages and sayings can be interpreted to have some direct meaning for all of us.

Over the years in our personal lives, we have been constantly advised that prevention is better than cure…certainly… Read More


Advanced CMOS/FinFET Fabrication

Advanced CMOS/FinFET Fabrication
by Semitracks Inc. on 04-30-2020 at 9:00 am

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known… Read More