TSMC Design Considerations for Gate-All-Around (GAA) Technology

TSMC Design Considerations for Gate-All-Around (GAA) Technology
by Tom Dillinger on 07-12-2021 at 6:00 am

mobility differences 3

The annual VLSI Symposium provides unique insights into R&D innovations in both circuits and technology.  Indeed, the papers presented are divided into two main tracks – Circuits and Technology.  In addition, the symposium offers workshops, forums, and short courses, providing a breadth of additional information.

At… Read More


VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm

VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm
by Scotten Jones on 07-02-2021 at 6:00 am

Figure 1

At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent… Read More


TSMC and the FinFET Era!

TSMC and the FinFET Era!
by Daniel Nenni on 06-09-2021 at 6:00 am

Intel 22nm wafer

While there is a lot of excitement around the semiconductor shortage narrative and the fabs all being full, both 200mm and 300mm, there is one big plot hole and that is the FinFET era.

Intel ushered in the FinFET era only to lose FinFET dominance to the foundries shortly thereafter. In 2009 Intel brought out a 22nm FinFET wafer at the… Read More


ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era
by Scotten Jones on 01-15-2021 at 6:00 am

Slide3

I was asked to give a talk at the 2021 ISS conference and the following is a write up of the talk.

The title of the talk is “Logic Leadership in the PPAC era”.

The talk is broken up into three main sections:

  1. Background information explaining PPAC and Standard Cells.
  2. A node-by-node comparisons of companies running leading edge logic
Read More

Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes

Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes
by Mike Gianfagna on 12-02-2020 at 10:00 am

Analog Bits is Supplying Analog Foundation IP on the Industrys Most Advanced FinFET Processes

The industry recently concluded a series of technology events for the all the major foundries.  Done as virtual events this year, each one provided a significant update on technology platforms, roadmaps and ecosystem partnerships. These events are quite valuable to chip design teams who need to be aware of the latest in process,… Read More


5G, Hyperscaling and the Resurgence of Consumer Silicon

5G, Hyperscaling and the Resurgence of Consumer Silicon
by Ramsay Allen on 10-04-2020 at 6:00 am

TSMC 5G OIP 2020

At the recent TSMC OIP Ecosystem Forum and Technology virtual events, TSMC re-affirmed their previous prediction that 5G is going to be a multi-year silicon mega-trend with the biggest drivers being the ramp up of 5G handsets, supporting infrastructure and the continued growth of high performance computing (HPC).

We all want… Read More


A “Super” Technology Mid-life Kicker for Intel

A “Super” Technology Mid-life Kicker for Intel
by Tom Dillinger on 08-17-2020 at 10:00 am

TigerLake WillowCove

Summary
At the recent Intel Architecture Day 2020 symposium, a number of technology enhancements to the Intel 10nm process node were introduced.  The cumulative effect of these enhancements would provide designs with a performance boost (at iso-power) approaching 20% – a significant intra-node enhancement, to be sure.  The… Read More


Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions

Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions
by Daniel Nenni on 07-29-2020 at 10:00 am

Globalfoundries AI Webinar Hiren Majmudar

I had the pleasure of spending time with Hiren Majmudar in preparation for the upcoming AI Accelerators webinar. As far as webinars go this will be one of the better ones we have done. Hiren has deep experience in both semiconductors and EDA during his lengthy career at Intel and now with a pure play foundry. He is intelligent, personable,… Read More


Staying on the Right Side in Worst Case Conditions – Performance (Part 2)

Staying on the Right Side in Worst Case Conditions – Performance (Part 2)
by Tim Penhale-Jones on 07-02-2020 at 10:00 am

Moortec Part 2 Talking Sense

In this, the second part of a two-part series we delve further into defining worst case, this time focusing specifically on device performance.

In the last blog we talked about the steady increase in power density per unit silicon area and how worst case is definitely getting worse. We discussed how in each new FinFET node the dynamic… Read More


Contact over Active Gate Process Requirements for 5G

Contact over Active Gate Process Requirements for 5G
by Tom Dillinger on 07-01-2020 at 6:00 am

frequency 5G

Summary
A recent process enhancement in advanced nodes is to support the fabrication of contacts directly on the active gate area of a device.  At the recent VLSI 2020 Symposium, the critical advantages of this capability were highlighted, specifically in the context of the behavior of RF CMOS devices needed for 5G designs.

IntroductionRead More