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Prototyping with Intel's New 80M Gate FPGA and S2C!

Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability

REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation

REPLAY: Avoiding CDM (Charged Device Model) ESD Failures

REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"

REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification

REPLAY: Fabless: The Transformation of the Semiconductor Industry

REPLAY: The Brave New World of Customized Memory

REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning

REPLAY: VLSI Design Methodology Development

REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved!

REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?

REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!

REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

REPLAY: Taiwan ESD Workshop Recording

REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction

REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)

REPLAY: Finding Your Way Through Verification

REPLAY: Concerned about IP security threats for your SoCs?

REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip

REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior

REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design

REPLAY: Choose the Right ASIC Manufacturing Model for Your Business
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Prototyping with Intel's New 80M Gate FPGA and S2C!

Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability

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REPLAY: Avoiding CDM (Charged Device Model) ESD Failures

REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"

REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification

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REPLAY: The Brave New World of Customized Memory

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REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?

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REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior

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October 11, 2019October 14, 2019

My Top Three Reasons to Attend IEDM 2019

My Top Three Reasons to Attend IEDM 2019
by Scotten Jones on 10-11-2019 at 6:10 am
Categories: Events, FD-SOI, FinFET, Foundries, Intel, TSMC

Image RemovedThe International Electron Devices Meeting is a premier event to learn about the latest in semiconductor process technology. Held every year in early December is San Francisco this years conference will be held from Decembers 7th through December 11th. You can learn more about the conference at their web site here… Read More

September 5, 2019September 17, 2019

TSMC OIP Overview and Agenda!

TSMC OIP Overview and Agenda!
by Daniel Nenni on 09-05-2019 at 6:00 am
Categories: Events, Foundries, TSMC

The TSMC Symposium and OIP Ecosystem Fourm are the most coveted events of the year for the fabless semiconductor ecosystem, absolutely. In my 35 years of semiconductor experience never has there been a more exciting time in the ecosystem and that is clear by the overview and agenda for this year’s event. I hope to see you there:… Read More

WEBINAR: VLSI Design Methodology Development

WEBINAR: VLSI Design Methodology Development
by Daniel Nenni on 09-04-2019 at 10:00 am

This webinar provides a brief overview of a new text, VLSI Design Methodology Development. The content of the book will be reviewed, highlighting topics that have recently influenced SoC design methodology features – e.g., FinFET circuit libraries, multipatterning lithography, layout-dependent effects, electromigration… Read More

August 28, 2019September 17, 2019

Webinar: VLSI Design Methodology Development (new text)

Webinar: VLSI Design Methodology Development (new text)
by Tom Dillinger on 08-28-2019 at 10:00 am
Categories: Events
1 Comment

Daniel Nenni was gracious enough to encourage me to conduct a brief webinar describing a new reference text, recently published by Prentice-Hall, part of the Semiwiki Webinar Series.

Image Removed

VLSI DESIGN Methodology Development Webiner Replay

Background

I was motivated to write the text to provide college students with… Read More

August 28, 2019September 17, 2019

IEDM 2019 to Highlight Innovative Devices for an Era of Connected Intelligence

IEDM 2019 to Highlight Innovative Devices for an Era of Connected Intelligence
by Scotten Jones on 08-28-2019 at 6:00 am
Categories: Events

Image RemovedThe IEEE International Electron Devices Meeting is in my opinion the leading technology conference to understand the current state-of-the-art in semiconductor process technology. Held each year in early December in San Francisco it is a must attend conference for anyone following technology development. The… Read More

May 16, 2019October 3, 2019

IC to Systems Era

IC to Systems Era
by Daniel Nenni on 05-16-2019 at 12:00 pm
Categories: Automotive, EDA, Events, FinFET, IROC Technologies, Mentor, a Siemens Business

One of my favorite EDA disruptions is the Siemens acquisition of Mentor, pure genius. Joe Sawicki now runs the Mentor IC EDA business for Siemens so we will be seeing him at more conferences and events than ever before. Joe did a very nice keynote at the recent U2U conference that I would like to talk about before we head to the 56thDAC… Read More

May 13, 2019September 11, 2019

The Evolution of the Extension Implant Part V

The Evolution of the Extension Implant Part V
by Daniel Nenni on 05-13-2019 at 7:00 am
Categories: Events, Semiconductor Services, Threshold Systems
1 Comment

Part 4 of this series discussed how a transistor Extension could be fabricated in a planar device without using an implant operation, and is instead formed using a preferential etch followed by a selective epitaxial deposition. This final installment of the series will present the formation of an Extension in a FinFET transistor… Read More

May 6, 2019September 11, 2019

The Evolution of the Extension Implant Part III

The Evolution of the Extension Implant Part III
by Daniel Nenni on 05-06-2019 at 7:00 am
Categories: Events, FinFET, Semiconductor Services, Threshold Systems

The problem of traditional FinFET Extension Implant doping concerns the awkward 3-dimensional structure of the fin. Because the Extension Implant defines the conductive electrical pathway between the Source/Drains and the undoped channel portion of the fin, it is essential that the fin be uniformly doped all three of its surfaces… Read More

May 2, 2019September 11, 2019

The Evolution of the Extension Implant Part II

The Evolution of the Extension Implant Part II
by Daniel Nenni on 05-02-2019 at 7:00 am
Categories: Events, FinFET, Semiconductor Services, Threshold Systems

The use of hard masks instead of photoresist for the Extension implant is an effective way to optimize the amount of dopant that is retained along the fin sidewalls for those fins that border along photoresist edges (as discussed in Part 1 of this series).

However, hard masks do nothing to address the dominant problem driving steeper… Read More

April 29, 2019September 11, 2019

The Evolution of the Extension Implant Part I

The Evolution of the Extension Implant Part I
by Daniel Nenni on 04-29-2019 at 7:00 am
Categories: Events, FinFET, Semiconductor Services, Threshold Systems
2 Comments

The 3D character of FinFET transistor structures pose a range of unique fabrication problems that can make it challenging to get these devices to yield. This is especially true for the all-important Extension implant that is put in place just prior to the nitride spacer formation.

The Extension implant is a central component of… Read More

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Why is Intel still short on chips?
Intel had to increase 14nm modem production from less than 40 million in 2018 to over 150M in 2019...............they never…

— Watson on December 8, 2019
Why is Intel still short on chips?
That's right.

— CrystalN on December 8, 2019
Why is Intel still short on chips?
https://translate.googleusercontent.com/translate_c?depth=1&rurl=translate.google.com&sl=auto&sp=nmt4&tl=en&u=https://www.chiportal.co.il/main-news/20-fabs-manufacturing-articles/7050-tsmc-announces-smart-man-machine-integration-0812192&xid=17259,15700023,15700186,15700191,15700256,15700259,15700262,15700265,15700271,15700283&usg=ALkJrhg4P0bnSS429wpRJwb2eWnGuFZj7w Tsmc is producing faster at a larger capacity and 14 in is an old tech. I think the whole…

— Portland on December 8, 2019
Why is Intel still short on chips?
More likely the design superstars from Apple and AMD are more than comfortable designing in TSMC and Samsung processes and…

— Rstar on December 8, 2019
Intel vs AMD vs Google vs Amazon vs NUVIA
https://www.ibm.com/cloud/power-virtual-server Just as an example. But even if it was not for such examples, IBM has been offering services such…

— kingmouf on December 7, 2019
Put Uber out of Our Misery
I never had a problem with uber. I just use it for going to work and food which is a…

— Portland on December 7, 2019
Put Uber out of Our Misery
Much of the so called gig economy is about the abuse of the law, the system and people that don't…

— Arthur Hanson on December 7, 2019
Put Uber out of Our Misery
FYI: Uber loses over $1 billion in market value after it reported 6,000 sex-assault cases https://www.yahoo.com/news/ubers-sex-assault-scandal-set-101852701.html

— Daniel Nenni on December 6, 2019
Put Uber out of Our Misery
Coincidently, my credit card was just flagged for suspicious activity. Multiple fraudulent Uber charges. They cancelled my card and are…

— Daniel Nenni on December 6, 2019
Put Uber out of Our Misery
I use uber and will still use it. It's tougher out there for women. It can be a toxic environment…

— Portland on December 6, 2019

Tag: finfet

My Top Three Reasons to Attend IEDM 2019

TSMC OIP Overview and Agenda!

WEBINAR: VLSI Design Methodology Development

Webinar: VLSI Design Methodology Development (new text)

IEDM 2019 to Highlight Innovative Devices for an Era of Connected Intelligence

IC to Systems Era

The Evolution of the Extension Implant Part V

The Evolution of the Extension Implant Part III

The Evolution of the Extension Implant Part II

The Evolution of the Extension Implant Part I

Upcoming Events

Open FinTech Forum

Seminar: Domain-Specific Processor Design...

Early AXI4 SOC Performance Verification...

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Qualcomm Moving Back to TSM

Pentagon Working with TSMC?

A Survey on Reliability of DNN Algorithms and Accelerators

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Why is Intel still short on chips?

Why is Intel still short on chips?

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