I will say that as popular as DO-254 and the like is, I am not the fella for that. It can take the simplest of designs into a realm of test and verification like you have never seen before. Yes, when I am flying I happen to be a big fan of this rigorous testing but you will not find me doing that job anytime soon. While the topic is very dry, it can be a very lucrative one for companies who have mastered the art of requirements writing and proving what is done and not done.
Some companies find themselves with lots of great technologies and solutions but are scared to move into the flight worthiness and safety critical realm, with good reason. They can either buy another company who knows that part of the business or get training. Monday, I had the privilege to sit through a free webinar from Aldec called “DO-254 Verification – Requirements Optimization for Verification”. Aldec knows a thing or two about this stuff and I highly recommend anyone or company who are venturing into this realm to consider Aldec.
Last month I wrote that Aldec is the DO-254 leader, let me expound just a bit more on why. Aldec knows, that the key for DO-254 success is great requirements. Notice I did not say good, but great. This can be the difference from being on track with cost and schedule or mega failure and potentially loss of lives in the extreme situations. No laughing matter. Below is a great slide from the free Aldec webinar.
I have ran into the issue of non-verifiable requirements. They involve lots of meetings, head hitting the wall, frustration, and much money wasted only to have the requirement changed. For us FPGA design weenies, requirement writing in the beginning can be a challenge. We want to implement everything. Aldec gives great guidance here… “Requirements should not describe how a circuit is designed or implemented”. What this means is to let go of some control here and trust the team to do their job while you do yours. An example is the output pin on the FPGA shall toggle at a frequency of 5 Hz, +/- 0.01% jitter and duty cycle when the FPGA is powered on. Notice I did not say you shall use DSP blocks, use LUTs etc… What is the cost of a bad requirement? Aldec quickly identifies this with the following slide below. Note all the expensive peer reviews.
So how does one get a handle on all this? Get training from Aldec and learn, learn, learn. Second, your team must believe the same mission, you cannot suffer to have a few cowboys on the team. All must understand their roles. This is critical. Third, tools. Get tools that will automate any part of the process and reduce the risk of human miscommunication and errors. Aldec has a ton of tools that can help with this process, but is not just limited to DO-254. They include Spec-TRACER, ALINT Design rule checking and of course DO-254/CTS. For example, you may be thinking why do I need LINT rule checking on my VHDL? To make the verification process easier and verifiable you must make sure that all names of the same subject have the same name. For Example what if in the FPGA you call reset ‘RSTn’, in the requirements ‘ResetNOT’, and in drawings ‘nRST’…? Yikes, that is no way to live. Use Aldec tools to make sure you are successful. You may also want to attend the seminar below for a thorough DO-254 training. It will set you apart from your competition for sure.