WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems

WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
by Daniel Nenni on 12-11-2023 at 10:00 am

Blog UPF Picture1

Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.

WEBINAR REGISTRATION

With the increasing complexity of such … Read More


Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology

Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology
by Daniel Nenni on 10-03-2023 at 6:00 am

blog sept pic1

With the increasing on-chip integration capabilities, large scale electronic systems can be integrated into a single System-on-Chip or SoC. New manufacturing test challenges are raised for more advanced technology nodes where both quality and cost during testing are affected. A typical parameter is test coverage which impacts… Read More


Defacto Celebrates 20th Anniversary @ DAC 2023!

Defacto Celebrates 20th Anniversary @ DAC 2023!
by Daniel Nenni on 07-05-2023 at 10:00 am

20ans signature clean

Defacto Technologies is a company that specializes in Electronic Design Automation (EDA) software and solutions. Defacto offers a range of EDA software solutions that help streamline and optimize various stages of the front-end design process. Their tools focus on chip design assembly and integration before logic synthesis

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Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy

Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy
by Daniel Nenni on 03-02-2023 at 6:00 am

SoC Integration IP XACT RTL

We have been working with Defacto since 2016 and it has been quite a journey. Putting an entire system on a chip is a driving force in the semiconductor industry. With the complexity of designing a modern SoC constantly increasing, new tools and methodologies are required and it all starts with RTL.

Defacto Technologies is an innovativeRead More


Podcast EP121: Managing Design Flows and EDA Resources with Innova

Podcast EP121: Managing Design Flows and EDA Resources with Innova
by Daniel Nenni on 11-11-2022 at 10:00 am

Dan is joined by Chouki Aktouf, founder & CEO of Defacto Technologies and co-founder of Innova Advanced Technologies. Prior to founding Defacto in 2003, Dr. Aktouf was an associate professor of Computer Science at the University of Grenoble – France and leader of a dependability research group. He holds a PhD in Electric Engineering… Read More


WEBINAR: What Makes SoC Compiler The Shortest Path from SoC Design Specification to Logic Synthesis?

WEBINAR: What Makes SoC Compiler The Shortest Path from SoC Design Specification to Logic Synthesis?
by Daniel Nenni on 05-24-2021 at 6:00 am

SoC compiler puzzle

Defacto SoC Compiler whose 9.0 release was announced recently automates the SoC design creation from the first project specifications. It covers register handling, IP and connectivity insertion at RTL, UPF and SDC file generation right to logic synthesis. As part of the generation process of RTL and design collaterals, basic… Read More


RTL Design Restructuring Explained

RTL Design Restructuring Explained
by Daniel Payne on 09-22-2016 at 4:00 pm

Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical… Read More