In-System Safety and Reliability for Automotive SoCs using Innovative Memory IP

In-System Safety and Reliability for Automotive SoCs using Innovative Memory IP
by admin on 07-01-2020 at 9:00 am

Synopsys Logo

In the emerging era of large scale SoCs comprised from complex IP, typically designed for AI and automotive applications, designers must embrace an innovative approach to overcome numerous safety and reliability challenges. Therefore, the solution must be scalable, robust and Functional Safety (FuSa) aware, in addition … Read More


WEBINAR: High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

WEBINAR: High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
by Daniel Nenni on 06-30-2020 at 10:00 am

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates.

Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential… Read More


Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals

Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals
by Daniel Nenni on 06-23-2020 at 10:00 am

Don’t miss this opportunity to hear from Synopsys’ IP senior executives and product experts on how to accelerate your high-performance computing SoC designs. Find out about the latest market trends that will help you make important design decisions. Learn how specific features of Synopsys’ IP enables you to achieve the required

Read More

WEBINAR: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

WEBINAR: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
by Daniel Nenni on 06-23-2020 at 10:00 am

Identifying glitches and revealing the extra power they consume require special attention to cell delays and wire delays. To enable earlier and more frequent analysis, physical-and-timing-aware glitch power analysis is needed throughout the flow from RTL to Signoff. In this webinar, we review the glitch power challenges … Read More


Design Technology Co-Optimization (DTCO) for sub-5nm Process Nodes

Design Technology Co-Optimization (DTCO) for sub-5nm Process Nodes
by Tom Dillinger on 06-23-2020 at 6:00 am

scaled metal resistance

Summary
Design Technology Co-Optimization (DTCO) analysis was pursued for library cell PPA estimates for gate-all-around (GAA) devices and new metallurgy options.  The cell design and process recommendations are a bit surprising.

Introduction
During the “golden years” of silicon technology evolution that applied Dennard… Read More


The New Frontier of Die-to-Die Interface IP: What You Need to Know for Silicon Success

The New Frontier of Die-to-Die Interface IP: What You Need to Know for Silicon Success
by Daniel Nenni on 06-16-2020 at 10:00 am

server room woman.jpeg.imgw .365.219

Don’t miss this opportunity to hear from Synopsys’ IP senior executives and product experts on how to accelerate your high-performance computing SoC designs. Find out about the latest market trends that will help you make important design decisions. Learn how specific features of Synopsys’ IP enables you to achieve the required

Read More

WEBINAR: Securing Your SoCs: Advanced Techniques for Security Verification

WEBINAR: Securing Your SoCs: Advanced Techniques for Security Verification
by Daniel Nenni on 06-16-2020 at 10:00 am

Security concerns permeate our digital lives. From online financial or personal data transactions, to automobile control and even election tampering, protecting access has become a critical necessity for almost all applications. With semiconductor hardware forming the foundation of modern electronic systems, a hack here… Read More


Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
by Mike Gianfagna on 06-16-2020 at 6:00 am

Screen Shot 2020 06 15 at 6.59.34 PM

I had the opportunity to preview an upcoming webinar from Synopsys on SoC Glitch Power – what it is and how to reduce it. There is some eye-opening information in this webinar. Glitch power is a bigger problem than you may think and Synopsys has some excellent strategies to help reduce the problem. The webinar is available via replay… Read More


Synopsys Announces IP Supporting 5G’s Game Changing Low Power IoT Spec

Synopsys Announces IP Supporting 5G’s Game Changing Low Power IoT Spec
by Tom Simon on 05-22-2020 at 6:00 am

5G NB IoT Processor from Synopsys

If you are like me, you will get a 5G phone because of the high bandwidth it offers. However, there is a lot more to 5G than just fast data. In fact, one of the appealing features of 5G is low bandwidth communication. This is useful for edge devices that perform infrequent and low volume data transfers and depend on long battery life. Prior… Read More


AI SoC Architectures for Smart, Efficient Edge Computing

AI SoC Architectures for Smart, Efficient Edge Computing
by admin on 04-30-2020 at 10:00 am

RonLowman20200403020618
The concept of edge computing—putting low power servers close to the application instead of relying solely on “the cloud”–may not be a novel idea, but for 5G and the Internet of Things, adding AI capabilities to edge computing will be revolutionary.  SoC designs will need to provide distributed intelligence in hardware
Read More