Webinar: Intel: Enabling and Evaluating Intel EMIB-T Bridging Design with Synopsys Tools

In this webinar, Intel will present how EMIB-T (Embedded Multi-die Interconnect Bridge with TSVs) enables compact, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share a production-oriented EMIB-T reference methodology built on Synopsys’ 3DIC Compiler platform that spans early planning through signoff. The webinar highlights how early bump and TSV planning, automated die‑to‑die routing for HBM and UCIe, and a unified exploration‑to-signoff data model help Intel manage system‑level co-design complexity while maintaining closure on timing, power, thermal, and SIPI. Intel will also discuss SIPI methodology using Synopsys Tools and EMIB-T’s ability to support dense, high-speed HBM interfaces.

What you’ll learn

• How EMIB-T addresses key multi-die design challenges
• Why early bump/TSV planning is critical for EMIB‑T success
• How automated die-to‑die routing accelerates convergence
• How a unified flow supports scalable timing, power, thermal, and SIPI signoff
• How EMIB‑T enables high‑speed HBM integration with confidence

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