hist78
Well-known member
News Summary:
“Ramping ‘Venice’ on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure,” said Dr. Lisa Su, chair and CEO, AMD. “As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster. Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment.”
As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of “Venice” comes as AMD continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments.
The “Venice” ramp in Taiwan and plans to ramp at TSMC Arizona reflect AMD’s focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, AMD is expanding the foundation needed to support customers as they deploy and scale AI infrastructure.
“We are pleased to see AMD continue to make strong progress with its next-generation EPYC processor on our advanced 2nm process technology,” said Dr. C.C. Wei, Chairman and CEO, TSMC. “Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing.”
AMD also plans to extend TSMC 2nm process technology across its data center CPU roadmap with “Verano,” a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, “Verano” is expected to build on the AMD EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications.
AMD and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC®-X and CoWoS®-L, used across AMD’s broader AI and data center portfolio. With “Venice” ramping on TSMC 2nm, AMD is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.
- AMD has begun production ramp of its 6th Gen AMD EPYC™ CPUs, codenamed “Venice,” marking a major milestone for the AMD and TSMC collaboration on 2nm technology
- “Venice” is the first HPC product in the industry to achieve production ramp on TSMC advanced 2nm technology
- Critical milestone achieved as agentic AI workloads drive demand for accelerated AI infrastructure deployments
- AMD continues to drive 2nm product expansion with “Verano” a follow on to “Venice” with industry leading integration of LPDDR for growing memory demand in agentic AI workloads
“Ramping ‘Venice’ on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure,” said Dr. Lisa Su, chair and CEO, AMD. “As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster. Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment.”
As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of “Venice” comes as AMD continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments.
The “Venice” ramp in Taiwan and plans to ramp at TSMC Arizona reflect AMD’s focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, AMD is expanding the foundation needed to support customers as they deploy and scale AI infrastructure.
“We are pleased to see AMD continue to make strong progress with its next-generation EPYC processor on our advanced 2nm process technology,” said Dr. C.C. Wei, Chairman and CEO, TSMC. “Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing.”
AMD also plans to extend TSMC 2nm process technology across its data center CPU roadmap with “Verano,” a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, “Verano” is expected to build on the AMD EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications.
AMD and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC®-X and CoWoS®-L, used across AMD’s broader AI and data center portfolio. With “Venice” ramping on TSMC 2nm, AMD is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.