3D IC Update from User2User

3D IC Update from User2User
by Daniel Payne on 05-24-2022 at 10:00 am

FO WLP min

Our smart phones, tablets, laptops and desktops are the most common consumer products with advanced 2.5D and 3D IC packaging techniques. I love seeing the product tear down articles to learn how advanced packaging techniques are being used, so at the User2User conference in Santa Clara I attended a presentation from Tarek Ramadan,… Read More


Bespoke Silicon is Coming, Absolutely!

Bespoke Silicon is Coming, Absolutely!
by Daniel Nenni on 04-18-2022 at 6:00 am

IMG 9977

It was nice to be at a live conference again. DesignCon was held at the Santa Clara Convention Center, my favorite location, which to me there was a back to normal crowd. The sessions I attended were full and the show floor was busy. Masks and vaccinations were not required, maybe that was it. Or there was a pent-up demand to get back engaged… Read More


Overcoming System-Level 3D-IC Electrical and Thermal Challenges

Overcoming System-Level 3D-IC Electrical and Thermal Challenges
by Admin on 04-06-2022 at 10:00 am

Overview

Electronics products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise.

Addressing these concerns through simulation during system planning and continuing through signoff will accelerate… Read More


Overcoming System-Level 3D-IC Electrical and Thermal Challenges

Overcoming System-Level 3D-IC Electrical and Thermal Challenges
by Admin on 04-06-2022 at 12:00 am

Overview

Electronics products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise.

Addressing these concerns through simulation during system planning and continuing through signoff will accelerate… Read More


3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hiearchical Analysis

3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hiearchical Analysis
by Admin on 03-23-2022 at 12:00 am

Overview

A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs).  Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis also is extremely… Read More


System Planning and Implementation for Different 3D-IC Design Styles

System Planning and Implementation for Different 3D-IC Design Styles
by Admin on 03-09-2022 at 12:00 am

March 9, 2022

Overview

System planning is a major part of the multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving

Read More

More Than Moore and Charting the Path Beyond 3nm

More Than Moore and Charting the Path Beyond 3nm
by Kalar Rajendiran on 12-22-2021 at 10:00 am

Cadence AIML Technologies

The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More


Ansys CEO Ajei Gopal’s Keynote on 3D-IC at Samsung SAFE Forum

Ansys CEO Ajei Gopal’s Keynote on 3D-IC at Samsung SAFE Forum
by Tom Simon on 12-09-2021 at 10:00 am

Ajei Gopal talks about 3D IC

System on chip (SoC) based design has long been recognized as a powerful method to offer product differentiation through higher performance and expanded functionality. Yet, it comes with a number of limitations, such as high cost of development.  Also, SoCs are monolithic, which can inhibit rapid adaptation in the face of changing… Read More


Ansys Multiphysics Platform

Ansys Multiphysics Platform
by Tom Dillinger on 07-26-2021 at 10:00 am

platform communication

Background
Traditionally, the interface between chip designers and system power, packaging, reliability, and mechanical engineering teams was a relatively straightforward exchange of specifications.  Chip designers developed preliminary power dissipation estimates, often based on a simplifying power/mm**2 value. … Read More


Driving PPA Optimization Across the Cubic Space of 3D IC Silicon Stacks

Driving PPA Optimization Across the Cubic Space of 3D IC Silicon Stacks
by Tom Simon on 07-06-2021 at 9:00 am

Improved PPA Using 3D IC

The move to true 3D IC, monolithic 3D SOC and 3D heterogeneous integration may require one of the most major design tool architecture overhauls since IC design tools were first developed. While we have been taking steps toward 3DIC with 2.5D designs with interposers, HBM, etc., the fundamental tools and flows remain intact in many… Read More