Accelerating 5G Design Innovation Through Simulation Workshop

Accelerating 5G Design Innovation Through Simulation Workshop
by Daniel Nenni on 01-22-2019 at 12:00 pm

Image RemovedDesignCon is coming up, kicking off the first of many industry conferences for the year. It’s at the Santa Clara Convention Center which is the best venue in Northern California. Not only is this a semiconductor crowd, it’s also a systems crowd covering chips, boards, and systems. More than 175 companies participate… Read More


HBM offers SOC’s dense and fast memory options

HBM offers SOC’s dense and fast memory options
by Tom Simon on 08-22-2017 at 7:00 am

Dual in-line memory modules (DIMM’s ) with double data rate synchronous dynamic random access memory (DDR SDRAM) have been around since before we were worried about Y2K. Over the intervening years this format for provisioning memory has evolved from supporting DDR around 1995, to DDR1 in 2000, DDR2 in 2003, DDR4 in 2007 and DDR4… Read More


Cadence Expands Integrated Photonics Beachhead

Cadence Expands Integrated Photonics Beachhead
by Mitch Heins on 03-30-2017 at 4:00 pm

Image RemovedIn November of 2016, I made a bold statement that October 20, 2016 would stand as a watershed day in integrated photonics. The reason for this claim was that GLOBALFOUNDRIES proclaimed that integrated photonics was real and here to stay. The same week I wrote an article about Cadence Design Systems securing a photonic… Read More


Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA

Join the Multi-die IC session on April 21 at EDPS 2016 in Monterey, CA
by Herb Reiter on 04-14-2016 at 12:00 pm

Following Moore’s Law down to 10 or even 7 nm labeled feature size demands US $ hundreds of millions of up-front investment, a very large design team and two or more years of development time. These parameters suggest that it only makes sense for very high volume applications to continue on the shrink path to increase SoCs’ functionalities.… Read More


2015 3D ASIP conference: Thar’s Gold in Them Thar Hills!

2015 3D ASIP conference: Thar’s Gold in Them Thar Hills!
by Bill Martin on 12-27-2015 at 4:00 pm

Image RemovedLast week I presented at the 3D ASIP EDA Tutorial and attended the Conference. In previous years, leading edge papers were presented from large companies pushing a solution to meet their needs. These companies had the resources and clout to achieve some astounding successes, but the lingering question was: “wh… Read More


Boost the Market for Interposer and 3D ICs with Assembly Design Kits

Boost the Market for Interposer and 3D ICs with Assembly Design Kits
by Beth Martin on 07-29-2015 at 6:00 pm

The traditional system-on-chip (SoC) design process has fully qualified verification methods embodied in the form of process design kits (PDKs). Why is it that chip design companies and assembly houses have no IC/package co-design sign-off verification process?
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Package die are often produced using multiple… Read More


Will 3DIC Ever Be Cheap Enough for High Volume Products?

Will 3DIC Ever Be Cheap Enough for High Volume Products?
by Paul McLellan on 12-12-2014 at 8:00 pm

Image RemovedMore news from the 3DASIP conference. Chet Palesko of SavanSys Solution had an interesting presentation with the same title as this blog (although this blog draws from several other presentations too). Chet took a look at what aspects of 3D are likely to get cheaper going forward. He took as a starting point that stuff… Read More


3D, The State of the State

3D, The State of the State
by Paul McLellan on 12-11-2014 at 8:00 am

I have been at the 3D ASIP conference that is held every year in Burlingame. It is far and away the best place to get a snapshot on what is going on in 3D (and 2.5D) IC design each year. One of the presentations was by the guys from Yole on where the industry is right now. Other presentations were on pathfinding, power reduction (did you know… Read More


3DIC in Burlingame

3DIC in Burlingame
by Paul McLellan on 12-01-2014 at 7:00 am

Image RemovedEvery year in December is what I think of as the main 3D IC conference where you can get up to speed on all the latest. Officially it is called 3D Architectures for Semiconductor and Packaging or 3D ASIP. It is held in the Hyatt Regency in Burlingame (the one right by 101 near the airport). This year it is from December 10-12th.… Read More


Solution for PI, TI & SI Issues in 3D-ICs

Solution for PI, TI & SI Issues in 3D-ICs
by Pawan Fangaria on 11-30-2014 at 7:00 pm

As we move towards packing more and more functionalities and increasing densities of SoCs, the power, thermal and signal integrity issues keep on rising. 3D-IC is a great concept to stack multiple dies on top of each other vertically. While it brings lot of avenues to package dies with multiple functions together, it has challenges… Read More