It was back in 1991 that Cadence first announced the Virtuoso product name, and here we are 32 years later and the product is alive and doing quite well. Steven Lewis from Cadence gave me an update on something new that they call Virtuoso Studio, and it’s all about custom IC design for the real world. In those 32 years we’ve seen the semiconductor process march along Moore’s Law from 600nm using planar CMOS, scaling down to the FinFET era below 22 nm, reaching GAA at the 3nm node. Clearly the EDA tool demands have changed as smaller nodes brought on new physical effects that needed to be modeled and simulated to ensure first silicon success.
The focus of Cadence Virtuoso Studio is to help IC designers take on the present day challenges through six areas:
- Increased process complexity
- Handling 10,000s of circuit simulations
- Design automation and circuit migration
- Heterogenous integration
- Sign-off, in-design verification and analysis
The Virtuoso ADE (Analog Design Environment) allows circuit engineers to explore their analog, mixed-signal and RFIC designs through schematic capture and circuit simulation. The architecture of Virtuoso ADE has been revamped for better job control, reducing RAM usage, and speeding up simulations by using the cloud. For one example the RAM required to run Spectre on 10,000s of simulations was reduced from 420MB down to just 18MB for simulation monitoring, while expression evaluations decreased from 420MB of RAM to just 280MB.
Updates to the Virtuoso Layout Suite include four choices of place and route technology, each suited to the unique task at hand through the Virtuoso environment:
Four P&R Technologies
- Custom Device Level – EM/IR aware auto routing, ModGen – template reuse
- Mature Node – Virtuoso Custom Router
- Standard Cell Blocks – Integrates with Innovus GigaPlace, NanoRoute
- Custom Digital – Virtuoso Custom Router, Virtuoso Space-Based Router
DRC and LVS runs are part of physical verification, and running these in batch mode, fixing and repeating, leads to long development schedules. In-design verification allows the interactive use of DRC and LVS while working on an IC layout, so feedback on what to change is quickly highlighted, accelerating productivity. A layout designer using Virtuoso Layout Suite benefits from in-design verification using the Pegasus DRC and LVS technology.
Chiplets, 2.5D and 3D packaging span the traditionally separate realms of PCB, package and IC design domains. Virtuoso Studio enables the co-design and verification of packages, modules and ICs by:
- Providing multi-PDK support
- Using a single golden schematic
- Having EM solvers that are integrated
- Working with Allegro Package Designer Plus
- Interoperable with AWR Microwave Office
Looking into the near future you can expect to see details emerge about how AI is being applied to automatically go from an analog schematic into layout based on machine learning and specifications. These auto-generated trial layouts will further speed up a very labor intensive process. A second development area for AI to be applied is the problem of migrating custom analog IP to a new process node. Stay tuned.
Early customers of Virtuoso Studio include Analog Devices for the co-design of IC and package, leading-edge IC consumer designs at MediaTek, and AI-based process migration at Renesas.
Virtuoso Studio has put into release 23.1 some impressive new features that IC design teams can start using to be more productive. The Virtuoso infrastructure has changed to meet the challenges of Moore’s Law, simulations with 10,000s circuit simulations are practical, RFIC and module 2.5D/3D co-design are supported, in-design DRC/LVS verification takes much less time, and AI is being applied to automate analog tasks.
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