CadenceTECHTALK: Static Timing Analysis and Some Important Basics

CadenceTECHTALK: Static Timing Analysis and Some Important Basics
by Admin on 01-16-2023 at 2:11 pm

Date: Thursday, January 26, 2023

Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST

Static Timing Analysis (STA) aims to validate the timing performance of a synchronous design. While it is a well-known concept in modern digital implementation flows, for engineers who are not familiar with STA or others who would like

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EDA Flows for 3D Die Integration

EDA Flows for 3D Die Integration
by Tom Dillinger on 07-20-2021 at 6:00 am

future integration

Background

The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures.  The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies. … Read More


Cadence Defines a New Signoff Paradigm with Tempus PI

Cadence Defines a New Signoff Paradigm with Tempus PI
by Mike Gianfagna on 07-20-2020 at 10:00 am

Screen Shot 2020 06 24 at 11.24.34 PM

Semiconductor technology advances have a way of rewriting the rule book. As process geometries shrink, subtle effects graduate to mainstream problems. Performance curves can become inverted. And no matter what else occurs, low power demands are constantly reducing voltage and design margins along with it. Sometimes these… Read More


Webinar: Extending Innovation with Innovus 20.1 Release (Hebrew)

Webinar: Extending Innovation with Innovus 20.1 Release (Hebrew)
by Admin on 05-26-2020 at 11:42 pm

Overview

The Cadence® Innovus™ Implementation System continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this webinar, Cadence will share the latest Innovus Implementation 20.1 release technology highlights.

Topics such as physically aware logic restructuring,

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Webinar: Investigating and Improving Clock Delays

Webinar: Investigating and Improving Clock Delays
by Admin on 05-26-2020 at 11:37 pm

Overview

As typical system-on-chip designs grow larger and move to the latest FinFET process nodes, clocking constraints become ever more complex. The Cadence® Innovus™ Implementation System’s CCOpt™ useful skew optimization engine is a powerful tool to close the timing on the latest high-speed designs. Understanding and

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Webinar: Extending Innovation with Innovus 20.1 Release

Webinar: Extending Innovation with Innovus 20.1 Release
by Admin on 05-26-2020 at 11:31 pm

Overview

The Cadence® Innovus™ Implementation System continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this webinar, Cadence will share the latest Innovus Implementation 20.1 release technology highlights.

Topics such as physically aware logic restructuring,

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The Complexity of Block-Level Placement @ 56thDAC

The Complexity of Block-Level Placement @ 56thDAC
by Tom Dillinger on 06-11-2019 at 10:00 am

The recent Design Automation Conference in Las Vegas was an indication of how the electronics industry is evolving.  In its formative years, DAC was focused on the fundamental algorithms emerging from academic research and industrial R&D, that enabled the continuation of the Moore’s Law complexity curve.  (Indeed, the… Read More


IoT Designs Beginning to Shift to 7nm: Promises Upside for Cadence Physically-Aware Design Flow

IoT Designs Beginning to Shift to 7nm: Promises Upside for Cadence Physically-Aware Design Flow
by Mitch Heins on 01-29-2018 at 12:00 pm

Until recently, ICs at bleeding edge nodes like 7nm technology from foundries like TSMC were mostly targeted for high-performance-computing (HPC) and mobile applications or possibly high radix switches that needed the increased performance of advanced nodes. The momentum of Moore’s law and Moore-than-Moore saw foundries… Read More


Extraction Features for 7nm

Extraction Features for 7nm
by Tom Dillinger on 08-21-2017 at 12:00 pm

Frequent Semiwiki readers are familiar with the importance of close collaboration between the foundries and EDA tool developers, to provide the crucial features required by new process nodes. Perhaps the best illustration of the significance of this collaboration is the technical evolution of layout parasitic extraction.… Read More


The CDNLive Keynotes

The CDNLive Keynotes
by Bernard Murphy on 04-25-2017 at 7:00 am

I’m developing a taste for user-group meetings. In my (fairly) recently assumed role as a member of the media, I’m only allowed into the keynotes, but from what I have seen, vendors work hard to make these fresh and compelling each year through big-bang product updates and industry/academic leaders talking about their work in bleeding-edge… Read More