The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures. The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies. … Read More
Semiconductor technology advances have a way of rewriting the rule book. As process geometries shrink, subtle effects graduate to mainstream problems. Performance curves can become inverted. And no matter what else occurs, low power demands are constantly reducing voltage and design margins along with it. Sometimes these… Read More
Overview
The Cadence® Innovus™ Implementation System continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this webinar, Cadence will share the latest Innovus Implementation 20.1 release technology highlights.
Topics such as physically aware logic restructuring,
Overview
As typical system-on-chip designs grow larger and move to the latest FinFET process nodes, clocking constraints become ever more complex. The Cadence® Innovus™ Implementation System’s CCOpt™ useful skew optimization engine is a powerful tool to close the timing on the latest high-speed designs. Understanding and
Overview
The Cadence® Innovus™ Implementation System continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this webinar, Cadence will share the latest Innovus Implementation 20.1 release technology highlights.
Topics such as physically aware logic restructuring,
The recent Design Automation Conference in Las Vegas was an indication of how the electronics industry is evolving. In its formative years, DAC was focused on the fundamental algorithms emerging from academic research and industrial R&D, that enabled the continuation of the Moore’s Law complexity curve. (Indeed, the… Read More
Until recently, ICs at bleeding edge nodes like 7nm technology from foundries like TSMC were mostly targeted for high-performance-computing (HPC) and mobile applications or possibly high radix switches that needed the increased performance of advanced nodes. The momentum of Moore’s law and Moore-than-Moore saw foundries… Read More
Frequent Semiwiki readers are familiar with the importance of close collaboration between the foundries and EDA tool developers, to provide the crucial features required by new process nodes. Perhaps the best illustration of the significance of this collaboration is the technical evolution of layout parasitic extraction.… Read More
I’m developing a taste for user-group meetings. In my (fairly) recently assumed role as a member of the media, I’m only allowed into the keynotes, but from what I have seen, vendors work hard to make these fresh and compelling each year through big-bang product updates and industry/academic leaders talking about their work in bleeding-edge… Read More
