I talked with Paul Cunningham (VP front-end digital R&D) at CDNLive recently to get a Cadence perspective on digital design trends. He sees needs from traditional semiconductor companies evolving as usual, with disruption here and there from consolidation. But on the system side there is explosion in demand – for wearables, furniture, grid and power delivery management and in many more domains. Since many of these teams are starting from a blank sheet, they’re looking (especially in Asia) for high-productivity front-to-back solutions that will get them running at full speed as fast as possible.
Everyone is squeezing cost and power and needs to build in security and delivery is (unsurprisingly) schedule-sensitive but other factors counter traditional expectations of IoT design. Devices are complex (now we have realized you can’t push all the heavy compute to the cloud), so they want to go to advanced nodes. Also system designers want to build a diverse range of solutions, therefore require flows that support fast turn-around without needing vast teams of engineers. In short, direct involvement from systems companies pushes the well-known problem even harder; design complexity and diversity continues to rise much faster than engineering resources, schedules are getting tighter and cost-sensitivity is climbing.
On turn-around time, physical synthesis has to handle 3-5X the number of gates in the same time which demands all kinds of fundamental changes for massive parallelism, for coupling to physical design and for handling advanced technologies. The Cadence Genus Synthesis Solution is now handling 3-5 million placeable instances in production designs and should already be scalable to 10+ million instances flat in overnight runs making it practical to optimize all but the largest IPs and even some sub-systems in single physical synthesis runs.
On high-productivity solutions, physical synthesis requires very accurate correlation between physical estimates at this stage and what will actually be implemented on physical design. You have to use the same placer, the same global router, the same extractor and the same delay calculator which is exactly what Genus does, sharing the same engines with the Innovus Implementation System.
But productivity is not just about engine correlation. Who among us didn’t curse Microsoft Office when Word, PowerPoint and Excel supported what should have been exactly the same features in different ways? Didn’t we feel more productive when those features became common? The same thing applies to design. Front-end and implementation designers need to be able to easily exchange bounding timing and physical constraints, timing reports and scripts without confusion between different flavors of format. Genus provides this again through deep engine integration with Innovus, even extending to report formats.
On cost-pressure, a major contributor to device unit-cost is test-time (which can be as much as 50% of unit cost). System and IoT applications are pushing to reduce this further by looking for even higher levels of test compression. Current compression approaches compress in effect linearly by splitting scan chains into multiple chains. Unfortunately, this increases routability problems since every scan chain must connect to compression logic. The result can be increased die area which puts the cost burden back on silicon. Effectiveness is also bounded by need to keep chains sufficiently long that they can deliver test patterns to test challenging cases.
Cadence recently announced a 2D-based elastic compression in the Modus Test Solution which through a grid-based approach can greatly reduce routing overhead; the elastic part represents the ability to borrow from previous test clock cycles to extend scan patterns for challenging test cases. Between these innovations, Modus allows for much higher levels of compression, reducing time on the tester, without bloating die area. Experience with production designs shows 2-3X reduction in test time with 2.6X reduction in routing overhead.