Until recently, ICs at bleeding edge nodes like 7nm technology from foundries like TSMC were mostly targeted for high-performance-computing (HPC) and mobile applications or possibly high radix switches that needed the increased performance of advanced nodes. The momentum of Moore’s law and Moore-than-Moore saw foundries continuing to invest in more aggressive nodes, but it left many wondering what markets (and associated IC volumes) would justify the investments needed for 7nm and below.
In the meantime, the internet-of-things (IoT) emerged, and with it came the need for highly heterogeneous IC architectures with multiple different processor cores, embedded memories, networks-on-chip (NoCs) and a variety of different sensors, actuators, and interfaces including wireless transceivers. Conventional wisdom had been that these designs would separate the analog/mixed-signal portions (e.g. analog sensors, radios, transceivers, etc.) onto separate die from the digital processing elements and then combine everything into Systems-in-a-Package (SiPs).
However, we’re starting to see a shift. IoT designs, for example, can potentially drive huge volumes and as such SiPs may be too costly, forcing designers to move to the bleeding-edge nodes to once again do it all on one chip. Similarly, IP companies that may have been making their own discreet analog/mixed-signal chips are being asked to integrate their IP into customer’s systems-on-chip (SoCs) to lower overall costs, especially in markets like mobile and IoT. Moving to nodes like 7nm enables designers to consolidate everything onto one die while achieving superior performance, lower overall system power and reduced piece part pricing. Viola, build it and they will come. It looks like the IoT market may end up making 7nm a node that hangs around for a long time. It’s a big gamble though as designing at 7nm is not for the faint of heart.
I recently spoke with David Stratman, DSG Product Management & Business Development manager at Cadence Design Systems. David confirmed that they have seen a dramatic upturn in the number of medium- and large-sized companies moving their mobile and IoT designs from more mature nodes straight to 7nm for the reasons mentioned above, and in turn requiring any digital or mixed signal subsystem IP providers do the same. These companies are looking to Cadence’s expertise at 7nm to help them make the transition into a very different design environment. Fortuitously, Cadence has been planning for this since its introduction of the first of their next-generation digital platform products (Ex: Innovus, Tempus, Genus).
Innovus initially took on 16nm challenges such as FinFET design including the use of colorization for multi-patterning. At 10nm, colorization became a full requirement and the tools also had to deal with increased wire resistance making interconnect layer selection more challenging. At 7nm, it becomes even more complex with the use of via-pillars to get access to device pins. In fact, the entire flow had to be re-engineered to take physical aspects of 7nm design into consideration from the very beginning of the flow through to tapeout.
In the past, there was a clear line of demarcation between logic design and physical design. For decades designers used flows made up of tools from multiple electronic design automation (EDA) vendors, passing data between tools through both standard and non-standard interfaces. Cadence is betting that this is going to start changing with the latest technology nodes, and their tool flow reflects it. Their digital platform starts with a foundation of common core engines and full-flow optimizations. The flows make use of shared code that uses stage-specific abstractions of the data. Shared engines include placement, routing, delay calculation, extraction, timing and power analysis. The idea is to make the flow more predictive from the very start of the design by taking physicality into account as early in the design flow as possible.
This physical-first design flow changes the way design is done. Physical context is leveraged throughout the flow to the point that there is no explicit hand-off between logic and physical design. The idea is to continuously converge on design closure with smaller iteration loops enabled by shared compute engines. This full-flow optimization is difficult to do when using tools from multiple EDA vendors and Cadence is betting that the difference will be significant enough to convince customers to use their tools for the entire flow. To give added incentive, Cadence also upgraded their tool architecture to take advantage of massively parallel compute resources. Not only is the tool flow more integrated and predictive, but it’s also able to handle vastly larger design blocks when dealing with compute-intensive analysis algorithms such as extraction, timing and power analysis and physical verification.
David shared some recent results from a stealth startup company. The company began using Cadence Innovus on their first 16nm project alongside other industry tools and moved to the full Cadence digital flow at 7nm because of the flow’s shared physically-aware scalable engines.Not only did the company see big improvements in individual tool runtimes (example: Distributed STA on 400M gates flat ran in 6.5 hrs vs 50+ hrs), they also saw a 2X improvement physical design turnaround time with the Cadence Genus-Spatial + Innovus flow vs their traditional flow.
Back to the IoT angle on this, Cadence also made sure that their digital flow now interfaces seamlessly with their Virtuoso-based mixed-signal and custom flow. That means that IoT designers have a direct path to integrating everything (digital and mixed-signal) they need on their SoC at the advanced design nodes. If IoT customers continue in a trend to jump to 7nm both Cadence and TSMC stand to greatly benefit from Cadence’s physical-first design flow.
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