DesignCon 2022 is back to a live conference, from Tuesday, April 5th through Thursday, April 7th, at the Santa Clara Convention Center.
DesignCon is a unique gathering in our industry. Its roots incorporated a focus on complex design and analysis requirements of (long-reach) high-speed interfaces. Technical presentations and vendor exhibits on the conference Expo floor spanned a wide variety of topics – e.g., SerDes Tx/Rx design methods; PCB interconnect and dielectric materials; cables and connectors for high-speed signals; EDA tools for PCB design, plus extraction and simulation of (strongly frequency-dependent) interconnect parameters.
World-renowned signal integrity (SI) and power integrity (PI) experts offered their insights into how to layout PCB busses and place power decoupling and DC blocking capacitors for improved SI/PI fidelity.
And, the conference Expo highlighted the latest in technical equipment for high-speed interface analysis (on reference boards), from oscilloscopes and signal generators to bit-error rate testers to spectrum analyzers and vector network analyzers.
As the complexity of system designs has grown, and as high-speed interface design has expanded to encompass short, medium, and long-range topologies, so too has DesignCon expanded.
The emphasis on the materials and properties of boards, cables, and connectors is still strong, to be sure. The introduction of 56Gbps and 112Gbps datarate standards (and pulse-amplitude modulated signal levels) has added to the focus on model extraction accuracy. The transition from simple IBIS Tx/Rx electrical elements to more complex IBIS-AMI functional plus electrical models has enabled comprehensive “end-to-end” simulations.
In addition to the evolution of these more demanding tasks, there are three key focus areas evident in this year’s DesignCon program.
- advanced 2.5D/3D packaging technology necessitates “full 3D” electromagnetic model extraction
Traditional rules-of-thumb used for early PCB layout definition of high-speed interface signals no longer apply to today’s system-in-package integration. Insertion loss guidelines in “dB per inch per GHz” have no significance in a 2.5D package with heterogeneous functionality, spanning very wide high bandwidth memory (HBM) busses to source-synchronous short-reach interfaces between die. The nature of this advanced packaging technology requires a full 3D extraction model for accurate analysis of insertion, reflection, and crosstalk behavior.
- tight integration between design and analysis tools is absolutely required
Traditional PCB and backplane-centric high-speed interface design didn’t offer many degrees of freedom – e.g., board layer materials and thicknesses, via topologies and types (through vias or backdrilled vias, for impedance control).
The development of a 2.5D package requires focus on interface planning, as an integral part of the initial design flow. The sheer number of interface connections and the disparity in their clocking and IL/RL/Xtalk requirements necessitates a tight design and analysis optimization loop. A PCB may be able to accommodate the insertion of a high-speed repeater (re-driver or re-timer) component later in the design cycle to address a failing signal spec. A 2.5D package design offers no such flexibility – it has to be “first time right”. The design and analysis workflow must offer fast, accurate results. In addition, there is typically very limited SI/PI expertise available to design companies – these workflows need to be available to many designers, based on a familiar EDA platform environment.
- IP offerings are critical to accelerating product introductions integrating advanced interface standards
The pace at which new interface definitions are being introduced is rapid. DesignCon has expanded to provide system developers with information on (silicon-proven, qualified) IP available for SoC integration.
Cadence at DesignCon
I recently had the opportunity to chat briefly with Sherry Hess at Cadence, to learn what new technologies Cadence will be presenting at this year’s DesignCon. Indeed, their focus is on new workflows, improved 2.5D/3D modeling accuracy, and advanced IP.
Here are some of the workflow-related presentation sessions.
- NO Exit Ramps Needed – Cadence’s System Design Workflow Delivers Seamless In-Design Analysis, Reducing Turnaround Time and Minimizing Risk
- Mainstream Signal Integrity Workflow for PCI 6.0 PAM4 Signaling
- Amphenol: 112G Connector and Board Design/Analysis Workflow
- Meta (Facebook): MIPI-C Board and Camera Interface Design/Analysis Workflow
- Microsoft: Interconnect Optimization of Wearables with an In-Design Analysis Workflow
Note that these presentations include collaborations with various other firms using these workflows, from component providers to systems companies.
Clarity 3D Solver Enhancements
The parametric model extraction of a 3D structure involves a tradeoff in accuracy versus computational resources. The complex nature of 3D geometries requires an intricate finite element mesh, whether for a system-in-package or multiple packages on a combination of rigid and/or flex substrates. The electromagnetic solver for the mesh is computationally demanding.
At DesignCon, Cadence will be demonstrating significant enhancements to their Clarity 3D solver, including:
- a new distributed meshing algorithm, with significant reduction in simulation runtimes
- a new machine-learning based algorithm for optimizing a “sweep” of design parameters
- workflow integration with Cadence Allegro (and Allegro Package Designer), Integrity 3D-IC, and Virtuoso RF platforms
It wasn’t long ago that 28Gbps was the emerging standard interface. Cadence will also be presenting their IP development for 224Gbps.
- The Future of 224G Serial Links
Appended below are DesignCon links of interest – at a minimum, if you are involved in functional and/or electrical interface design, from system-in-package to long-reach signaling, you should definitely get a FREE Expo pass. And, be sure to stop by the Cadence Expo booth for product demonstrations and more technical information.