Ever since the cost of development started growing exponentially, engineering teams have been deploying a shift-left strategy to software development and system verification. While this has helped contain cost and accelerated product development schedules, a shift-left strategy is not without challenges. A virtual platform methodology is a common approach to implement a shift-left strategy. The platform is expected to fully represent the functionality of a target system-on-chip (SoC) or a board-based system.
With systems getting more and more complex, it takes a long cycle time to completely finalize the system. Thus, a virtual platform will not be able to accurately represent the full system until the system itself is finalized. So, developers pull together abstract models of various subsystems and components of the system to produce a virtual platform. The goal is to help make progress on the software development front. But in reality, many projects delay their virtual platform initiative until the hardware is reasonably implemented. With this being the bottleneck, having access to emulators and FPGA prototyping system resources doesn’t change the situation much.
Can something be done to leverage a virtual platform methodology earlier than what may be commonly practiced today? This was the focus of a talk, delivered at DVCon 2022. The following is a synopsis of the salient points from that talk by Ross Dickson and Pankaj Kakkar. Both work at Cadence where Ross is a product management director and Pankaj is a solutions group director in the System & Verification Group. They present details of how to improve system verification by using virtual platforms as a software-driven methodology.
Hybrid Platform Approach
The idea is to extract the value of a virtual platform and the values of emulation and FPGA prototyping systems at the earliest possible opportunity. With most systems, the competitive differentiation lies within a portion of the entire design. Let’s say, for example, that a custom accelerator is a key differentiator in a system. Of course, the system will have some kind of CPU core, a modem for communication, some I/Os, etc. Even if the specific CPU core for the system is not finalized yet, knowing whether it’s Arm or RISC-V and whether it’s 64-bit or 32-bit would be very useful. Picking something that is about right is better than a completely abstract model. With access to an extensive library of reference designs, one can start off with a virtual platform that is not completely abstract and virtual.
With this approach, the team designing the custom accelerator can work with a hybrid platform that is more realistic for its purposes. And the team working on integrating with the CPU core has its hybrid platform that is more realistic for its purposes. Other teams may be working on I/Os and drivers. As the different teams refine and finalize their respective blocks/sub-systems, those are swapped into the virtual platform. Finally, all pieces are integrated to provide the complete system. While this doesn’t happen until late in the design flow, the various teams have been productive throughout.
If the detailed RTL already exists for a portion of a design, then the user can put that into an emulator or FPGA prototyping system. And integrate that with the virtual platform for a hybrid platform that leverages verification hardware solutions.
Cadence® Helium™ Virtual and Hybrid Studio
The Cadence® Helium™ Virtual and Hybrid Studio provides a unified embedded software experience with native integration to Cadence’s Xcelium™, Palladium® and Protium™ verification engines. It includes an integrated debugger and comes with an entire library of reference designs. Pankaj walked the audience through the process of building a new hybrid platform from the base reference platform. Users can select various models from the extensive library of models that come with Helium and configure the model parameters as needed. They can also remove unwanted models from the platform and then handle the port bindings, interconnections and memory mappings. For more details, visit the product page.
Pankaj then walked the audience through a typical hybrid platform creation flow, which enables software debug on Helium and runs Linux. The audience saw a live demo of the Helium hybrid platform in action and its various features.
The Helium software debugger is a standard Eclipse-based software debugger that provides all the basic features that any debugger would provide. Refer to the figure below for the debugger window. Through this GUI, users can see all the critical information.
With Cadence’s Helium Virtual and Hybrid Studio, users can increase their verification throughput and produce a better system more easily than through a traditional development methodology. This enables early pre-silicon software bring-up and hardware/software co-verification.
The Dickson-Kakkar DVCon talk can be accessed here by registering at the DVCon website.
The Dickson-Kakkar DVCon presentation slides can be downloaded here.
Learn more about the Helium Virtual and Hybrid Studio.
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