About DVCon China
DVCon China is a technical conference in China targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon China is similar to the successful DVCon… Read More
Tag: dvcon
DVCon U.S.
The Design and Verification Conference (DVCon) is the leading event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon brings chip architects, design and verification … Read More
DVCon Is a Must Attend Event for Design and Verification Engineers
Learning is a never-ending process for design and verification engineers, so outside of reading SemiWiki you likely want to attend at least a few events per year to keep updated, learn something new, attend a workshop, or even present something that has made your IC project work much better than before. Sure, DAC is always a great… Read More
Deep Learning, Reshaping the Industry or Holding to the Status Quo
AI, Machine Learning, Deep Learning and neural networks are all hot industry topics in 2019, but you probably want to know if these concepts are changing how we actually design or verify an SoC. To answer that question what better place to get an answer than from a panel of industry experts who recently gathered at DVcon with moderator… Read More
Surviving in the Age of Digitalization
There was an interesting keynote at DVCon last month. It was titled “Thriving in the Age of Digitalization” which introduced the concept of digital twins for design and production. It was presented by Fram Akiki who is a relative newcomer to EDA but has an interesting history so I will start there.
Fram and I got started in the semiconductor… Read More
AI, Deep Learning, SystemC, UVM, PSS – DVCon Has it All
Today I had the pleasure to speak with Tom Fitzpatrick, TPC Chair for the DVCon conferenceand exhibition slated for February 25-28 in the heart of Silicon Valley – San Jose. Tom lives in Massachusetts, a place where I used to live and work at Wang Labs, back in the day before the PC and WordPerfect software ended Wang’s… Read More
DVCon is coming in February, now is the time to register early
As 2018 wraps up this month it’s time to start thinking and planning for 2019, and if you work in the Silicon Valley then you’ll want to consider adding the 31st annual DVCon event planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on a SoC project… Read More
Don’t Stand Between The Anonymous Bug and Tape-Out (Part 1 of 2)
In the EDA space, nothing seems to be more fragmented in-term of solutions than in the Design Verification (DV) ecosystem. This was my apparent impression from attending the four panel sessions plus numerous paper presentations given during DVCon 2018 held in San Jose. Both key management and technical leads from DV users community… Read More
Anirudh on Verification
I was fortunate to have a 1-on-1 with Anirudh before he delivered the keynote at DVCon. In case you don’t know the name, Dr. Anirudh Devgan is Executive VP and GM of the Digital & Signoff Group and the System & Verification Group at Cadence. He’s on a meteoric rise in the company, not least for what he has done for Cadence’s position… Read More
Mentor gets Busy at DVCon
You’d expect Mentor to be covering a lot of bases at DVCon and you wouldn’t be wrong. They’re hosting tutorials, a lunch, papers, posters, there’s a panel and of course they’ll be on the exhibit floor. I’ll start with an important tutorial that you really should attend, Monday morning, on creating Portable Stimulus Models… Read More
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