DVCon Europe 2024by Admin on 02-26-2024 at 7:18 pm
About DVCon Europe
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe… Read More
Accellera at DVCon US 2024
Authors:
- Jean-Philippe Martin, Intel
- Mike Borza, Synopsys
Topic(s): Security
Keywords: security, asset, accellera, sa-edi, IEEE P3164, threat modeling
Abstract: This workshop will demonstrate how to identify assets in intellectual property (IP) in accordance with Accellera’s Security Annotation… Read More
The Accellera UVM Working Group released the IEEE 1800.2-2020-2.0 reference library last year. Since that release, we have been working on a public Github repository to give users enhanced access to the latest bug fixes and to provide bug fix suggestions if they would like. Also, we have developed new, additive features to… Read More
Accellera at DVCon US 2024
Abstract:
Join Accellera for an informative luncheon focused on the efforts and direction of the Federated Simulation Standard Proposed Working Group (FSS PWG). The luncheon will begin with an update on Accellera working group activity from Chair Lu Dai, followed by the presentation of a Distinguished… Read More
Accellera at DVCon US 2024
Abstract:
As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This tutorial covers the proven clock domain crossings (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential… Read More
Accellera at DVCon US 2024
Speaker:
- Richard Weber, Fellow, Director of Engineering, Arteris
- Anupam Bakshi, CEO, Agnisys
Introduction: This tutorial explains basic usage of IP-XACT IEEE 1685-2022 for IP re-use and integration flows.
Summary:
This workshop explains the data model underlying the IP-XACT standard. This SoC… Read More
Accellera at DVCon U.S. 2024
Efficient Portable Programming – Sequence Development with PSS
Bringing an SoC-level system out of reset into an operational state involves configuring the component subsystems and IPs by properly programming hundreds or thousands of IP registers. Running behavior involves programming… Read More
Axiomise pioneered the adoption of formal verification in the semiconductor industry since 2017. Led by visionary CEO, Dr. Ashish Darbari, who has 63 patents in formal verification, and Neil Dunlop an industry veteran with 40 years of experience, Axiomise has helped twenty customers over the last six years by providing them… Read More
