Deep Learning, Reshaping the Industry or Holding to the Status Quo

Deep Learning, Reshaping the Industry or Holding to the Status Quo
by Daniel Payne on 04-25-2019 at 12:00 pm

AI, Machine Learning, Deep Learning and neural networks are all hot industry topics in 2019, but you probably want to know if these concepts are changing how we actually design or verify an SoC. To answer that question what better place to get an answer than from a panel of industry experts who recently gathered at DVcon with moderator… Read More


Surviving in the Age of Digitalization

Surviving in the Age of Digitalization
by Daniel Nenni on 03-18-2019 at 7:00 am

There was an interesting keynote at DVCon last month. It was titled “Thriving in the Age of Digitalization” which introduced the concept of digital twins for design and production. It was presented by Fram Akiki who is a relative newcomer to EDA but has an interesting history so I will start there.

Fram and I got started in the semiconductor… Read More


AI, Deep Learning, SystemC, UVM, PSS – DVCon Has it All

AI, Deep Learning, SystemC, UVM, PSS – DVCon Has it All
by Daniel Payne on 02-14-2019 at 12:00 pm

Today I had the pleasure to speak with Tom Fitzpatrick, TPC Chair for the DVCon conferenceand exhibition slated for February 25-28 in the heart of Silicon Valley – San Jose. Tom lives in Massachusetts, a place where I used to live and work at Wang Labs, back in the day before the PC and WordPerfect software ended Wang’s… Read More


DVCon is coming in February, now is the time to register early

DVCon is coming in February, now is the time to register early
by Daniel Payne on 12-12-2018 at 7:00 am

As 2018 wraps up this month it’s time to start thinking and planning for 2019, and if you work in the Silicon Valley then you’ll want to consider adding the 31st annual DVConevent planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on a SoC project… Read More


Don’t Stand Between The Anonymous Bug and Tape-Out (Part 1 of 2)

Don’t Stand Between The Anonymous Bug and Tape-Out (Part 1 of 2)
by Alex Tan on 03-09-2018 at 7:00 am

In the EDA space, nothing seems to be more fragmented in-term of solutions than in the Design Verification (DV) ecosystem. This was my apparent impression from attending the four panel sessions plus numerous paper presentations given during DVCon 2018 held in San Jose. Both key management and technical leads from DV users communityRead More


Anirudh on Verification

Anirudh on Verification
by Bernard Murphy on 03-13-2017 at 7:00 am

I was fortunate to have a 1-on-1 with Anirudh before he delivered the keynote at DVCon. In case you don’t know the name, Dr. Anirudh Devgan is Executive VP and GM of the Digital & Signoff Group and the System & Verification Group at Cadence. He’s on a meteoric rise in the company, not least for what he has done for Cadence’s position… Read More


Mentor gets Busy at DVCon

Mentor gets Busy at DVCon
by Bernard Murphy on 02-20-2017 at 12:00 pm

You’d expect Mentor to be covering a lot of bases at DVCon and you wouldn’t be wrong. They’re hosting tutorials, a lunch, papers, posters, there’s a panel and of course they’ll be on the exhibit floor. I’ll start with an important tutorial that you really should attend, Monday morning, on creating Portable Stimulus Models… Read More


VC Apps Tutorial at DVCon 2016

VC Apps Tutorial at DVCon 2016
by Bernard Murphy on 03-17-2016 at 7:00 am

We might wish that all our design automation needs could be handled by pre-packaged vendor tool features available at the push of a button, but that never was and never will be the case. In the language of crass commercialism, there may be no broad market for those features, even though you consider that analysis absolutely essential.… Read More


Verdi Update and NVIDIA on Verification Compiler

Verdi Update and NVIDIA on Verification Compiler
by Bernard Murphy on 03-11-2016 at 12:00 pm

Synopsys hosted a lunch session on Thursday of DVCon. Michael Sanie of Synopsys opened the session, with a look back at the last DVCon where he had talked about Verification Compiler (VC) and extending the platform to Verification Continuum, which adds emulation and FPGA-based prototyping (HAPS – there was a very cool HAPS demo… Read More


Mentor at DVCon – Visualize This

Mentor at DVCon – Visualize This
by Bernard Murphy on 03-10-2016 at 12:00 pm

Steve Bailey entertained us during lunch on Tuesday with a talk on debug and visualization in the Mentor platform. Steve is based in Colorado, so had to spend the first part of his talk gloating about their Super Bowl win, but I guess he deserves that.

On a more technical note, he showed us a familiar survey they had completed with the… Read More