All Things Semiconductor!
AI, Machine Learning, Deep Learning and neural networks are all hot industry topics in 2019, but you probably want to know if these concepts are changing how we actually design or verify an SoC. To answer that question what better place to get an answer than from a panel of industry experts who recently gathered at DVcon with moderator… Read More
Image RemovedThere was an interesting keynote at DVCon last month. It was titled “Thriving in the Age of Digitalization” which introduced the concept of digital twins for design and production. It was presented by Fram Akiki who is a relative newcomer to EDA but has an interesting history so I will start there.
Fram and I got started… Read More
Today I had the pleasure to speak with Tom Fitzpatrick, TPC Chair for the DVCon conferenceand exhibition slated for February 25-28 in the heart of Silicon Valley – San Jose. Tom lives in Massachusetts, a place where I used to live and work at Wang Labs, back in the day before the PC and WordPerfect software ended Wang’s… Read More
As 2018 wraps up this month it’s time to start thinking and planning for 2019, and if you work in the Silicon Valley then you’ll want to consider adding the 31st annual DVCon event planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on a SoC project… Read More
Image RemovedIn the EDA space, nothing seems to be more fragmented in-term of solutions than in the Design Verification (DV) ecosystem. This was my apparent impression from attending the four panel sessions plus numerous paper presentations given during DVCon 2018 held in San Jose. Both key management and technical leads from… Read More
I was fortunate to have a 1-on-1 with Anirudh before he delivered the keynote at DVCon. In case you don’t know the name, Dr. Anirudh Devgan is Executive VP and GM of the Digital & Signoff Group and the System & Verification Group at Cadence. He’s on a meteoric rise in the company, not least for what he has done for Cadence’s position… Read More
You’d expect Mentor to be covering a lot of bases at DVCon and you wouldn’t be wrong. They’re hosting Image Removedtutorials, a lunch, papers, posters, there’s a panel and of course they’ll be on the exhibit floor. I’ll start with an important tutorial that you really should attend, Monday morning, on creating Portable Stimulus… Read More
We might wish that all our design automation needs could be handled by pre-packaged vendor tool Image Removedfeatures available at the push of a button, but that never was and never will be the case. In the language of crass commercialism, there may be no broad market for those features, even though you consider that analysis absolutely… Read More
Synopsys hosted a lunch session on Thursday of DVCon. Michael Sanie of Synopsys opened the session, Image Removedwith a look back at the last DVCon where he had talked about Verification Compiler (VC) and extending the platform to Verification Continuum, which adds emulation and FPGA-based prototyping (HAPS – there was a very… Read More
Steve Bailey entertained us during lunch on Tuesday with a talk on debug and visualization in the Mentor Image Removedplatform. Steve is based in Colorado, so had to spend the first part of his talk gloating about their Super Bowl win, but I guess he deserves that.
On a more technical note, he showed us a familiar survey they had completed… Read More
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Concerned about IP security threats for your SoCs?
Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
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Concerned about IP security threats for your SoCs?
Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
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REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
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better_recent_comments-2
Widget_Better_Recent_Comments Instance: 2Array
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Widget_Better_Recent_Comments
Response to IP’s Growing Impact On Yield And Reliability