Probing UPF Dynamic Objects

Probing UPF Dynamic Objects
by Tom Simon on 01-28-2021 at 6:00 am

Probing UPF Dynamic Objects

UPF was created to go beyond what HDL can do for managing on-chip power. HDLs are agnostic when it comes to dealing with supply & ground connections, power domains, level shifters, retention and other power management related elements of SoCs. UPF fills the breach allowing designers to specify in detail what parts of the design… Read More


SystemC Methodology for Virtual Prototype at DVCon USA

SystemC Methodology for Virtual Prototype at DVCon USA
by Daniel Payne on 07-13-2020 at 10:00 am

Register Model min

DVCon was the first EDA conference in our industry impacted by the pandemic and travel restrictions in March of this year, and the organizers did a superb job of adjusting the schedule. I was able to review a DVCon tutorial called “Defining a SystemC Methodology for your Company“, given by Swaminathan Ramachandran… Read More


Learning to Live with the Gaps Between Design and Verification

Learning to Live with the Gaps Between Design and Verification
by Tom Simon on 04-09-2020 at 6:00 am

Learning to live with the gaps between design and verification

Whenever I am asked to explain how chip design works by someone who is unfamiliar with the process, I struggle to explain the different steps in the flow. It also makes me aware of the discrete separations between each phase of activities. Of course, when you speak to a novice it is not even possible to get more than one layer down in the… Read More


DVCon Is a Must Attend Event for Design and Verification Engineers

DVCon Is a Must Attend Event for Design and Verification Engineers
by Daniel Payne on 02-03-2020 at 10:00 am

dvcon 2020

Learning is a never-ending process for design and verification engineers, so outside of reading SemiWiki you likely want to attend at least a few events per year to keep updated, learn something new, attend a workshop, or even present something that has made your IC project work much better than before. Sure, DAC is always a great… Read More


Deep Learning, Reshaping the Industry or Holding to the Status Quo

Deep Learning, Reshaping the Industry or Holding to the Status Quo
by Daniel Payne on 04-25-2019 at 12:00 pm

AI, Machine Learning, Deep Learning and neural networks are all hot industry topics in 2019, but you probably want to know if these concepts are changing how we actually design or verify an SoC. To answer that question what better place to get an answer than from a panel of industry experts who recently gathered at DVcon with moderator… Read More


Surviving in the Age of Digitalization

Surviving in the Age of Digitalization
by Daniel Nenni on 03-18-2019 at 7:00 am

There was an interesting keynote at DVCon last month. It was titled “Thriving in the Age of Digitalization” which introduced the concept of digital twins for design and production. It was presented by Fram Akiki who is a relative newcomer to EDA but has an interesting history so I will start there.

Fram and I got started in the semiconductor… Read More


AI, Deep Learning, SystemC, UVM, PSS – DVCon Has it All

AI, Deep Learning, SystemC, UVM, PSS – DVCon Has it All
by Daniel Payne on 02-14-2019 at 12:00 pm

Today I had the pleasure to speak with Tom Fitzpatrick, TPC Chair for the DVCon conferenceand exhibition slated for February 25-28 in the heart of Silicon Valley – San Jose. Tom lives in Massachusetts, a place where I used to live and work at Wang Labs, back in the day before the PC and WordPerfect software ended Wang’s… Read More


DVCon is coming in February, now is the time to register early

DVCon is coming in February, now is the time to register early
by Daniel Payne on 12-12-2018 at 7:00 am

As 2018 wraps up this month it’s time to start thinking and planning for 2019, and if you work in the Silicon Valley then you’ll want to consider adding the 31st annual DVCon event planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on a SoC project… Read More


Don’t Stand Between The Anonymous Bug and Tape-Out (Part 1 of 2)

Don’t Stand Between The Anonymous Bug and Tape-Out (Part 1 of 2)
by Alex Tan on 03-09-2018 at 7:00 am

In the EDA space, nothing seems to be more fragmented in-term of solutions than in the Design Verification (DV) ecosystem. This was my apparent impression from attending the four panel sessions plus numerous paper presentations given during DVCon 2018 held in San Jose. Both key management and technical leads from DV users communityRead More


Anirudh on Verification

Anirudh on Verification
by Bernard Murphy on 03-13-2017 at 7:00 am

I was fortunate to have a 1-on-1 with Anirudh before he delivered the keynote at DVCon. In case you don’t know the name, Dr. Anirudh Devgan is Executive VP and GM of the Digital & Signoff Group and the System & Verification Group at Cadence. He’s on a meteoric rise in the company, not least for what he has done for Cadence’s position… Read More