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AI, Deep Learning, SystemC, UVM, PSS – DVCon Has it All

AI, Deep Learning, SystemC, UVM, PSS – DVCon Has it All
by Daniel Payne on 02-14-2019 at 12:00 pm

Today I had the pleasure to speak with Tom Fitzpatrick, TPC Chair for the DVCon conferenceand exhibition slated for February 25-28 in the heart of Silicon Valley – San Jose. Tom lives in Massachusetts, a place where I used to live and work at Wang Labs, back in the day before the PC and WordPerfect software ended Wang’s fortunes. We swapped stories about the first Personal Computers, and computer languages starting from BASIC all the way up to Python.

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DVCon spans four days, so let’s take a look at the highlights so that you can focus on what interests you most about IC design and verification.

Monday
AI and Deep Learning permeate our technical literature daily and there’s good reason for that, just consider that the VC companies are backing hundreds of start-ups in this emerging area. John Aynsley of Doulousleads a short workshop from 1:45PM to 3:15PM titled, “Deep Learning for Engineers“. Vision and speech recognition are the two biggest application areas that I hear about for deep learning. John’s career started out in 1980 at Plessey where he developed their VHDL simulator, and he’s the CTO and co-founder of Doulos.

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Verification engineers know about Cliff Cummings, because he’s an expert at SystemVerilog and a developer of UVM. At Sunburst Designthey teach engineers best practices. This year his tutorial has perhaps the longest title ever, “Gain Valuable Insight into the Changes and Features that are part of the new IEEE 1800.2 Standard for UVM and how to make the most of them“. It’s best to learn good habits for a new language from a master, instead of grasping at how to be efficient on your own.

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Lunchtime is sponsored by Acellera and they have a Technical Excellence Award, but you must be present to hear about the winner, no spoilers allowed. A panel discussion covers the SystemC language with distinguished panelists from: Mentor, Synopsys, Cadence and NVIDIA.

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Tuesday
I was surprised to learn that there are 33 technical committee members, and they culled through over 100 submissions, selecting 39 papers and 25 poster topics. So you’ll want to check out the Opening Sessionto hear from the Steering Committee as they announce the Best Paper Award.

Three notable verification papers in the morning include:

  • Formal Verification Methodologies, Sean Sarfarpour, Synopsys
  • Verification Strategies I, Greg Tumbush, EM Microelectronics
  • Analog/Mixed-Signal Verification, Logie Ramachandran, Accelver Systems Inc.

With 25 Poster Sessions this year you can choose from timely topics and chat with the authors to increase your skillset:

  • Low power design and verification
  • Python
  • SystemVerilog
  • SystemC
  • UVM
  • PSS

The Keynote for Tuesday comes from a familiar systems company, Siemens PLM Software,as Fram Akiki shares his vision, “Thriving in the Age of Digitalization“. He covers all of the hot topics: AI, ML, 5G, IoT, autonomous vehicles.

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Harry Foster has conducted studies about functional verification over the years and shares that in a special session, “Trends in Functional Verification: A 2016 Industry Study“. Verification has become more of a software problem, and not so much a hardware problem. The verification process and effort can actually be more complex than the design.

In between sessions, keynotes and posters you should set aside some time to check out the vendors on the Expo floor.

| Agnisys
| Aldec
| Altair Engineering
|-
| AMIQ EDA
| Avery Design Systems
| Blue Pearl Software
|-
| Breker Verification
| Cadence
| CircuitSutra
|-
| DINI Group
| Doulos
| EDACafe.com
|-
| ESD Alliance
| FormalSim
| MathWorks
|-
| Methodics
| Metrics
| OneSpin
|-
| Oski
| Pro Design
| Semifore
|-
| Sigasi
| Sintegra
| SmartDV
|-
| Symbiotic
| Synopsys
| Truechip
|-
| Verific
| Werifyter
| Vtool

Wednesday

RISC V has grown rapidly in building market awareness for Open Source ISA, but how do you verify all of these new cores coming out? There’s a panel for that, “Verification and Compliance in the era of open ISA – Is the Industry ready to Address the Coming Tsunami of Innovation?“.

PSS, CDC and emulation are covered in the morning, and should be quite popular this year.

Is deep learning applied to verification just hype or reality? The panel with folks from AMD, Arm, Mythic, Achronix and NVIDIA will keep you informed.

Drum roll please, and the winner of this year’s Best Paper and Best Poster Session awards go to… Well, show up and hear Tom Fitzpatrick announcement at 4:45PM in the Bayshore Ballroom. It’s an honor and a testimony to all of the hard work that goes into the design and verification of billion transistor chips, something not financially or technically viable even five years ago.

Thursday
On the final day of DVCon is where you get to learn something new and useful to your engineering career by attending the six tutorials with presenters from leading companies:

  • Cadence
  • UltraSoC
  • Axiomise
  • Synopsys
  • Mentor
  • Verilab
  • Breker
  • Willamette HDL 

    Summary
    DVCon is a healthy and growing conference, so expect to see some 700 attendees during your time of networking, sessions, keynotes and exhibits. Receive the proceedings as PDF documents once you get registered, and if you Tweet then use the #DVCon_US to let us know what is most interesting this year.

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