DVCon is coming in February, now is the time to register early

DVCon is coming in February, now is the time to register early
by Daniel Payne on 12-12-2018 at 7:00 am

As 2018 wraps up this month it’s time to start thinking and planning for 2019, and if you work in the Silicon Valley then you’ll want to consider adding the 31st annual DVConevent planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on a SoC project than design does, so it makes sense to find out what’s new for verification engineers through:

  • 39 Technical papers
  • 25 Poster sessions
  • Two Panel discussions
  • Four Tutorials
  • Eight Short workshops

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The Accellera Systems Initiative is the sponsor for DVCon, and they grind out the much needed standards so that our industry doesn’t get polarized by proprietary and conflicting software automation approaches.

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The Universal Verification Methodology (UVM) can track its history from the Open Verification Methodology (OVM) and even the e Reuse Methodology (eRM) from Verisity back in 2001. Cliff Cummings leads a tutorial on Monday, February 25th all about UVM:

  • “Gain Valuable Insight into the Changes and Features that are Part of the New IEEE 1800.2 Standard for UVM and How to Mae the Most of Them”

Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world class Verilog, SystemVerilog, UVM Verification and synthesis training. Mr. Cummings is an independent consultant and trainer with 33 years of ASIC, FPGA and system design experience and 23 years of Verilog, SystemVerilog, synthesis and methodology training experience. Mr. Cummings has completed many ASIC designs, FPGA designs and system simulation projects, and is capable of answering the very technical questions asked by experienced design engineers.

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For keynote this year you’ll hear about the topic of the “Thriving in the Age of Digitalization” from Fram Akiki, VP Electronics & Semiconductor Industry for Siemens PLM Software. Fram’s background includes 21 years at IBM spanning roles in analog IC design, microprocessor manager and GM. His next 13 years were at Qualcomm as a director of operations, then head of the mobile computing connected products.

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There’s a buzz around all things RISC-V, so check out the panel discussion on Wednesday, February 27th entitled, “Verification and Compliance in the era of open ISA- is the Industry ready to Address the Coming Tsunami of Innovation?“. Moderator Mike Demler is a Senior Analyst at The Linley Group, and the panelists include:

  • Emerson Hsiao, Andes Technology
  • Adnan Hamid, Breker Verification Systems, Inc.
  • Rob Shearer, Facebook
  • Simon Davidmann, Imperas Software Ltd.
  • Neil Johnson, XtremeEDA Corp.

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Neil Johnson is active on Twitter and his tweets are focused on functional verification.

Networking throughout the conference is available during the Expo on Monday from 5PM to 7PM, then again on Tuesday and Wednesday from 2:30PM to 6PM. View the complete agenda online here, and register online now to get the best prices.

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.