No matter how high the processing capability of a chip, its overall performance is limited by IO speed. This is very similar to a car with low performance tires, a powerful engine will not be able to transfer its energy to the ground effectively. There is quite literally a race going on between core processing and IO speeds for transferring data on and off of chips. AI, autonomous vehicles, 5G and other advances are pushing a never-ending drive to increase data transfer rates.
One interesting area of innovation is in cell towers, where the radios used to sit in a box on the ground and high power RF signals were carried over copper to the antennas. This architecture created power and cooling problems among others. Common Public Radio Interface (CPRI) uses optical cables to carry the digitized RF signal to an RF power amplifier on the cell tower mast. Interestingly when this happened, carriers realized that they could architect their fronthaul to move the Base Band Units (BBUs) to or near the central office. The BBUs rely on high speed data links to get their job done.
Another area of innovation is the advent of Top Rack (TOR) switching. While it shortened the distance from server blades to the data switches, it also comes with a huge upward demand in transfer rates. The pivotal player in all these and many other changes in data transmission paradigms is the ubiquitous SerDes. Big changes have been needed to move from 28G to 56G and 112G and at the same time to limit cross talk and noise as the number of lanes increases.
High speed SerDes are needed not just for short reach connections, the demand for longer lines adds more consideration in SerDes Design. Other requirements for SerDes are back compatibility for lower data rates andlegacy protocols, and the ability to support copper and fiber. eSilicon, a leading provider of complex FinFET ASICs, has put out an interesting article discussing the complexities of designing SerDes for the leading-edge ASICs they deliver. This is in part due to their presence in the networking, AI and 5G markets as silicon a provider.
In their article, they touch on the need to move to PAM4 from the older PAM2/NRZ operation. Multiple bit-levels add complexity, with level detection made more difficult due to switching levels closer to threshold voltages. The leading edge SerDes, operating at 56G and 112G, are both digital and analog, making their design a challenging prospect.
eSilicon also talks about the increased need for on-chip testing and verification features. They have added full speed digital and analog loopback, and also a variety of smart monitoring features. With all this said, eSilicon has 7nm SerDes that are proven in silicon.
Innovation is needed to keep up with the demands for moving data. Ethernet is moving from 100GbE to 400GbE. The data rates for CPRI, mentioned above, are pushing upward from 25Gb/s to 50Gb/s. Back planes and data centers are soon going to be running at 25.6 and 51.2 Tb/s. More data sources, more data consumers, faster networks and high volumes of video and audio real-time data are all pushing technology forward. The eSilicon paper on 56G and 112G SerDes is pretty interesting and worth reading through to get an idea of what is needed to make fast chips move data effectively.Share this post via: