We all know IP is critical for advanced ASIC design. Well-designed and carefully tested IP blocks and subsystems are the lifeblood of any advanced chip project. Those IP suppliers who can measure up to the need, especially at advanced process nodes, will do well, absolutely.
It is interesting to note that eSilicon now has a very large internal IP group that is both developing IP and qualifying external IP to ensure there are no design spins and recently eSilicon has taken the mandate for quality IP to a new level.
A few weeks ago they announced neuASIC™, a 7nm IP platform for AI/deep learning that was covered by SemiWiki. This platform aims to make it easier to track changing AI algorithms in silicon by offering a library of configurable subsystems that can be easily assembled in an “ASIC chassis” – a kind of pre-defined architecture. This kind of approach takes IP quality, compatibility and configurability to a new level.
eSilicon is expanding their IP platform strategy this week. This time it’s a 7nm IP platform targeted at networking and switching ASICs for the data center. In this market, algorithms don’t change that much since everyone is designing to a standard protocol. What is challenging for these designs is hitting ultra-high-performance demands at a commercially acceptable power and density. To get that done requires a lot of tuning and trade-offs and that’s where eSilicon’s networking platform comes in.
All the elements of the platform have configurability built in, making it easier to perform the balancing act required to hit the power, performance and area requirements for advanced networking applications. All IP in the platform is “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. That also helps with integration and configuration. eSilicon complements their extensive library of IP with third-party offerings for the more commoditized functions, such as PCI Express PHYs, controllers, PLLs and PVT monitors. What is interesting is that eSilicon claims all the third-party IP in the platform adheres to the same compatibility and integration rules.
So what’s in the networking platform? Here’s a summary of the key parts:
At the core of the platform is eSilicon’s SerDes technology – communicating between chips is critical for these applications and the SerDes block is what does that. eSilicon’s design is based on a novel DSP-based architecture. Two 7nm PHYs support 56G and 112G NRZ/PAM4 operation to provide the best power efficiency tradeoffs for server, fabric and line-card applications. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane. A multitude of protocols are supported including Ethernet and Fibre Channel. The architecture allows scaling power consumption even further for shorter-reach channels. eSilicon claims a lot more capabilities and innovations for their SerDes technology. You can check out their website to find out more.
TCAMs are a big part of the platform and a big part of networking ASICs as well. Unlike a regular memory that returns the value stored in a given address, a TCAM returns all the addresses where a given value is stored. This comes in handy for packet processing applications. eSilicon has delivered 12 generations of TCAM technology and the current 7nm compiler supports low-power operation with partial-pipelined search, resulting in power savings. BIST enhancements allow faster design cycles and simulation through soft programming. A patented Duo architecture and two-cycle read/write architecture reduce area and power even further for large networking ASICs.
A lot of data center ASICs use HBM memory stacks to provide a large amount of storage that is easily accessible by the ASIC. These devices use a 2.5D integration scheme for the HBM memory stacks, so the PHY, or physical interface to those stacks is a key element of the power and performance profile. eSilicon has an HBM PHY (gen 2) as part of the platform as well. eSilicon’s HBM2 PHY integrates unique features to minimize switching noise and duty cycle distortion to provide a risk-free, robust solution. The PHY is a self-contained, hardened macro that offers many programmable hooks to architects. Drive strength calibration and jitter reduction as well as dedicated circuitry for training and lane repair are offered as well. eSilicon also has a 2.5D HBM enablement package. Based on seven years of experience with 2.5D design, this package provides easy integration of the HBM2 PHY and associated HBM2 DRAM stacks.
Rounding out the platform is an array of unique, network-optimized, high-speed and ultra-high-density memory compilers, register files and latch-based compilers optimized for extreme density and performance.