I recently watched a webinar given by eSilicon about its project to enhance its licensable solution for 56 and 112 Gigabit per second PAM4 & NRZ DSP-based SerDes family in 7nm. I am sure it was complicated enough to coordinate a webinar with a host, a moderator, and three different technical presenters – however when we are talking about 56 Gigabits per second and beyond in performance, in comparison, the webinar is as easy as a walk in the park. In some systems the number of SerDes lanes is approaching 300, system power is exploding, and legacy backplanes simply won’t work. This was never going to be easy.
Mike Gianfagna, eSilicon’s VP, Marketing was the host and opened the webinar. Dan Nenni of SemiWiki then acted as moderator and gave some opening comments. Following that was Al Neves, CTO of Wild River Technology, who was responsible for designing the test board to measure and deliver the needed performance and compliance. Then came Matt Burns, Product Marketing Manager–High Speed for Samtec, who discussed what was done to deliver the required connectivity. After that was Tim Horel, Director of Field Applications from eSilicon, who talked about putting it all together with eSilicon’s SerDes. To wrap it up there was a Q&A session where I imagine not all questions could be handled during the webinar, but I would expect eSilicon, given their high customer service standards, to follow up on any remaining questions offline. Though the session was not short, it moved quite quickly given all the information to cover.
Wild River Technology implemented the test board design. Al Neves spoke about the challenges to be faced in this area. Al and Wild River are the world’s experts when it comes to signal and power integrity for high-speed designs. They have been delivering high-speed designs to many companies for a long time and they have not lost their touch. Moreover, prior experience with these exotic waveforms is critical to solving the challenges that come up in this area, especially if you intend to deliver on time. Clearly, Wild River Technology had delivered.
Samtec also brought a lot to the table. eSilicon had determined to build the core of the design around Samtec’s Bulls Eye® Test Point System. This advanced cabling solution met the necessary high signal and power integrity requirements. Importantly, Samtec and Wild River made a great team as the project required a close working relationship between the cable solution provider (Samtec) and the board designer (Wild River). Samtec’s models also proved to be quite accurate, enabling a more predictable schedule.
As Tim Horel got into the specifics of the project, including utilizing some ideas Al Neves had proposed on how to run the project to develop this solution, I must admit I was having a hard time keeping up. This stuff is simply hard. Experts are needed. It shows how semiconductor IP has accelerated the semiconductor market. Few companies, maybe none really, can have all the expertise in every area in-house. Buying or licensing proven IP is the best solution for both making schedule and staying under budget.
If this stuff interests you, or if you simply want to learn more about this bleeding-edge technology, the webinar replay, and a white paper is available by going here. eSilicon has edited down the replay to 30 minutes, so you can learn a lot with a small investment of time. The eSilicon product description of eSilicon’s 56G & 112G PAM4 & NRZ DSP-Based Long-Reach SerDes Family in 7nm can be found here. Interesting and educational – have fun!