Having just completed a cloud evaluation for SemiWiki I can tell you why eSilicon chose Google. Simply put, they are working harder to get cloud business. Google ($4B) is the number five cloud provider behind Microsoft ($21.2B), Amazon ($20.4B), IBM ($10.3B) and Oracle ($6.08B). There is a lot of money in the cloud and a lot more to come which is why cloud providers are designing their own chips and partnering with ASIC providers like eSilicon to get that competitive edge. Speaking of ASICs in the cloud:
eSilicon Signs Multi-Year Agreement with Google Cloud
Under the terms of the agreement, Google Cloud will provide support from their professional services team to assist eSilicon as it moves its ASIC and IP design workloads to GCP. eSilicon has been running a hybrid on-premise/cloud environment for approximately the last 18 months, with ASIC design running on premise and IP design running primarily on GCP. This new agreement paves the way for a complete migration of all design activity to GCP.
“Google Cloud has demonstrated the resources, technical depth and domain knowledge to successfully move IC design to GCP, a significant undertaking,” said Naidu Annamaneni, CIO & vice president of global IT at eSilicon. “There are many unique requirements to support this kind of workload on the cloud and the need to collaborate with several infrastructure vendors to create the complete solution. Google Cloud possessed the domain knowledge and operational focus, backed by a substantial worldwide computing capability to get the job done.”
“Moving to the cloud provides the flexibility to build the right compute environment for each design project, resulting in improvements in time-to-market and design quality,” said Mike Gianfagna, vice president of marketing at eSilicon. “This is a substantial project with a lot of innovation and many partners. We’ll be talking more about this fast-paced program at it unfolds over the coming months.”
The big news here is that eSilicon is committing to move ALL ASIC and IP design to the Google Cloud Platform (GCP). They have been operating in a hybrid cloud environment for about a year and a half and now they are taking the next big step. Most of the chip design cloud activity today is hybrid so eSilicon is blazing trails here.
When it’s all said and done, there will be very few computers left inside eSilicon with all major infrastructure served in a flexible, cost effective, and highly secure way with GCP. Cost and security is critical but it’s the flexibility that makes the cloud a no-brainer for chip designers.
Remember, chip design is spiky in regards to compute resources. Processor speed, memory and storage requirements can vary a great deal, especially during the tapeout phase. There is no way an on-premise server farm can be competitive with a cloud offering during a tape-out. eSilicon can now apply the required compute resources needed to meet schedules, perform rigorous verification and deliver world-class ASICs. This ability to apply massive compute resources only when needed is unique to the cloud. The result is a higher quality design and all-important first-time-right silicon which is a make-or-break for the ultra competitive ASIC business.
The downside of the cloud is that you get what you ask for so you had better be careful what you ask for. For example, SemiWiki cloud resource requirements are easily predicted. Google cloud load balancing is as simple as adding a CPU, memory, or disk in a matter of clicks. eSilicon on the other hand is applying machine learning algorithms for an intelligent orchestration layer that assesses the need of a specific design project in regards to compute resources. It also manages costs based on project budgets from IP to full chip design. Expert resource management is a normal part of the ASIC business but with ML and the cloud it will be a completely different type of business, absolutely.
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com