Sandra Rivera, Chair of VSORA, joined Bloomberg’s The Close in July for an interview on the current state of AI. What follows is a summary of that conversation.
When a Silicon Valley veteran who once ran Intel’s Data Center and AI Group, and now chairs a French inference-chip challenger, sits down with a tech journalist from Bloomberg,… Read More
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Neural rendering. Offloading overloaded NPUs. Protection against evolving AI models. Developer-friendly programming. Reduced system complexity. There are many reasons why edge AI systems benefit from a GPU that delivers fast, efficient and fully programmable AI acceleration.… Read More
It’s that time of year again. Time certainly flies when AI is chasing you! This year marks the 18th TSMC OIP Ecosystem Forum, and it promises to be bigger and better than ever. My SemiWiki partners, Mike Gianfagna and Kalar Rajendiran, will join me in covering the event live, so stay tuned for all the news that’s fit to print.
Mike and… Read More
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For packaging, thermal, and mechanical engineers who need trusted warpage insight before stackup, material, and package architecture decisions are locked — and want to see what becomes possible when a full design study fits in an afternoon.
In advanced packaging, warpage is rarely a modeling… Read More
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Studies show that nearly 20% of the verification cycle is spent on assertion generation, debugging, and methodology integration — work that remains largely manual today or is delegated to general-purpose LLMs that hallucinate more than 30% of the time and produce incorrect assertions.… Read More
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A purpose-built multi-agent system for chip design shouldn’t be a quarter-long project. On the Agentrys Studio Platform, the initial build takes about 30 minutes—plus however much customization your flow and data require.
In this hands-on session, we’ll build a working end-to-end… Read More
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Full-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms, logs, and across hundreds of thousands of lines of code.
In this webinar, we will demonstrate… Read More
A single bug on a full-chip SoC can pull engineers off roadmap work for days or even weeks. It involves massive waveforms, thousands of files of RTL and UVM, and dense specs that aren’t always perfect. Finding these bugs have always been a matter of engineer-hours and how well knowledge diffuses through the organization.
Bronco … Read More
I believe DAC 2026 will be remembered as the turning point for AI assisted design. There has been discussion about AI infusion in EDA for a while now. Most of it was about how AI can be added to traditional tools to make existing methodologies better. This year, that changed. There were several new companies that highlighted a fundamentally… Read More
The “Silicon Shield” describes the idea that Taiwan’s central role in advanced semiconductor manufacturing raises the economic and strategic cost of military action against the island. The shield is not a literal defense system. It is a form of structural deterrence created by technological concentration: governments and… Read More
