A robust, proven library of IP is a critical enabler for the entire semiconductor ecosystem. Without it, ASIC design is pretty much impossible, given time-to-market pressures. Said another way, designing IP for your next chip simply doesn’t fit the schedule – most teams have barely enough time to integrate and validate pre-existing IP. Without solid IP coverage, new process nodes also become somewhat irrelevant for the same reasons. So, designers and foundries care about IP a lot.
7nm is where a lot of the action is these days regarding IP delivery. Datacenter, networking, AI and 5G infrastructure all have a thirst for the power and performance delivered by this node. So, there are lots of claims out there regarding 7nm IP. “World’s first, industry-leading, silicon-proven, robust” are just some of the words you’ll find in all the marketing material available for 7nm IP. The question is, how do you separate the hype from reality, and more importantly how do you truly reduce risk?
Simulation results, silicon data and number of tape outs are all important parts of the homework needed to find IP that is truly “robust”. Lately, there is another dimension to the problem worth considering as well. Beyond the IP working in silicon, does all the IP work well together? Before you bet the farm on your next 7nm design project, are you confident that all the IP will play well together? A completely validated library of IP can still cause huge headaches of it all doesn’t work together. Integration risks are very real, as are the risks associated with modifying IP to hit the required power, performance or area target.
The concept of IP that works well together and supports customization for a target application makes a lot of sense. Recently, eSilicon announced two such IP offerings for data center and AI chips, which SemiWiki covered here. eSilicon calls the concept an “IP platform”. I’m sure other marketing terms will emerge.
Recently, there have been a couple of announcements from eSilicon that bring these platforms closer to home. It turns out a high-performance SerDes is a critical enabler for both platforms. Last week, eSilicon announced very encouraging results from the silicon validation of its 56G 7nm SerDes. Their press release stated: “… lab measurements confirm that the design is meeting or exceeding the target performance, power and functionality. Based on these results eSilicon has begun to demonstrate its test chip to key customers.” So, contact eSilicon if you want to see what their SerDes can do, first hand.
This week, eSilicon announced that theirneuASICä platformis available for customer designs. Some detail about the what’s in neuASIC were disclosed:
“The neuASIC IP platform has been through several 7nm tapeouts. The platform includes the following compiled, hardened and verified functions:
- Configurable multiply-accumulate (MAC) blocks
- Single-port SRAM
- Pseudo two-port and pseudo four-port SRAM
- Ternary content-addressable memory
- Pitch match memory
- GIGA memory
- WAZPS (word all zero power saving) memory
- Transpose memory
- Re-mapper – low power cross-bar
- Convolution engine
- 56G SerDes
- HBM2 PHY
The platform also provides a software AI Accelerator Builder function that provides PPA estimates of the chosen ASIC architecture before RTL development starts.”
So, another reason to contact eSilicon if you’re considering a 7nm AI ASIC. I would check out both of these platforms if you want to reduce integration risks, absolutely.