CEO Interview: Deepak Kumar Tala of SmartDV

CEO Interview: Deepak Kumar Tala of SmartDV
by Daniel Nenni on 06-22-2020 at 10:00 am

SmartDV CEO Interview 2020

SMARTDV is one of the biggest small EDA companies in the industry today in regards to products, customers and number of licenses in use, absolutely.  They have a portfolio of more than 600 Design & Verification Solutions, everything from Design & Verification IP to Formal Verification IP, Post-Silicon Verification… Read More


Fractal CEO Update 2020

Fractal CEO Update 2020
by Daniel Nenni on 06-16-2020 at 10:00 am

Fractal Technologies SemiWiki

Rene Donkers, the company’s Co-founder and CEO, started his EDA career at Sagantec where he became responsible for world wide customer support and operations management. Ten years ago, Rene and a handful of people noticed a need in the design community for a standardized (portable) IP Validation approach to replace internal… Read More


Talking Sense With Moortec…Speak No Evil!

Talking Sense With Moortec…Speak No Evil!
by Tim Penhale-Jones on 06-08-2020 at 10:00 am

Speak no Evil Moortec

In the first of this blog trilogy, Talking Sense with Moortec…’Are you listening’,  I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time. In the second, Talking Sense with Moortec…’See no evil’, we bizarrely saw how Sir Francis Drake, Admiral Nelson and Clint… Read More


PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support

PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support
by Mike Gianfagna on 05-28-2020 at 10:00 am

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A couple of months ago I introduced PLDA, a new member of the SemiWiki community, with a post about PLDA’s switch IP and its support for PCIe and NVMe solid state disks. Working in the area of high-performance data interconnects requires support for a growing list of standards, standards that continually evolve. The trick is to stay… Read More


Filling the ASIC Void – Part 2

Filling the ASIC Void – Part 2
by Mike Gianfagna on 04-03-2020 at 6:00 am

Screen Shot 2020 03 24 at 5.00.49 PM

I concluded my last post on the topic with an inventory of the key attributes needed to fill the ASIC void created by the relentless consolidation in semiconductors. There were five items, as follows:

  1. Design and manufacturing expertise in a market that requires custom chips
  2. Differentiating IP and the skills to integrate it into
Read More

Filling the ASIC Void – Part 1

Filling the ASIC Void – Part 1
by Mike Gianfagna on 03-27-2020 at 6:00 am

shutterstock 235025512

It started slowly at first.  Then it began picking up steam. I’m referring to consolidation in the semiconductor sector. I had a front-row seat for what consolidation did to the ASIC part of semiconductor and that is the topic of this discussion. I was the VP of marketing at eSilicon, the company that invented the fabless ASIC model.… Read More


WEBINAR: Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud

WEBINAR: Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud
by Daniel Nenni on 03-19-2020 at 10:00 am

interlaken webinar banner semiwiki

Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken has found a unique spot as the protocol of choice for low latency, high throughput… Read More


Talking Sense With Moortec – The Future Of Embedded Monitoring Part 2

Talking Sense With Moortec – The Future Of Embedded Monitoring Part 2
by Stephen Crosher on 02-28-2020 at 10:00 am

Stephen Crosher Moortec CEO Square High Res

The rate of product development is facing very real challenges as the pace of silicon technology evolution begins to slow. Today, we are squeezing the most out of transistor physics, which is essentially derived from 60-year-old CMOS technology. To maintain the pace of Moore’s law, it is predicted that in 2030 we will need transistors… Read More


SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!

SiFive is Teaming with Many of the Most Prestigious Universities in South America to Engage Academia in the RISC-V Ecosystem!
by Swamy Irrinki on 11-14-2019 at 2:00 pm

We’re confirming seats in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga for the South American leg of our worldwide 2019 SiFive Tech Symposiums and Workshops. These five events will be focused heavily on academia, which is a key focus for SiFive. In fact, we are co-hosting these events with many of the most prestigious… Read More


DAC 2020 – Call for Contributions

DAC 2020 – Call for Contributions
by Daniel Payne on 10-28-2019 at 6:00 am

57DAC in SFO

My first DAC was in 1987 so I’ve seen our industry expand greatly over the years, and I expect that #57DAC on July 19-23, 2020 in SFO to be another exciting event to attend for semiconductor professionals from around the globe. What makes DAC so compelling for me to visit are the people, exhibitors, panel discussions, technical… Read More