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eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips

eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips
by Randy Smith on 08-13-2019 at 10:00 am

Figure 1: NeuASIC Platform Architecture

In early May of this year, eSilicon announced the tape-out of a test chip which included the latest additions to its neuASIC™ IP platform. At the upcoming Hot Chips Symposium to be held at Stanford on August 19 and 20, 2019, eSilicon will be demonstrating the software component of this AI-enabling IP platform. At the event, eSilicon will be giving live demonstrations of its AI Accelerator tool.  Late registration is still available for the event. The day before the symposium, various tutorials will be available at the same location. For more information on attending the Hot Chips, check the event website.

I learned first-hand of eSilicon’s ASIC design expertise more than 17 years ago when 2Wire, which had licensed the TriMedia VLIW core from me, asked me to find them help in designing their chip. I made the introduction to Jack Harding, eSilicon’s CEO, so I felt responsible for the success of that chip. eSilicon came through wonderfully and the chip, which became the engine inside AT&T’s initial UVerse residential gateway device, became enormously successful. Nearly two decades later, TriMedia has spun back into Philips Semiconductor (who then got acquired), 2Wire is now part of Pace, and AT&T is still a substantial player in the residential internet market – while eSilicon has continued to grow and is now much more than just a fabless ASIC company. Their capabilities and expertise now extend into 2.5D packaging, high-value IP (see my recent blog on their PAM4 SerDes IP) and more.

The neuASIC platform seeks to fill a void in the ASIC market for machine learning. Some of the reasons given for the challenges of an ASIC solution for this segment is that AI/ML algorithms are seemingly in near-constant flux. This uncertainty has made it difficult to design an ASIC chip and know that it will still be appropriate by the time the final product is to be shipped.

The neuASIC platform, available in 7nm FinFET technology, addresses this challenge with a modular design methodology. The solution provided utilizes a library of AI-specific tiles (i.e., macroblocks) that are quickly and easily configured to support the designer’s AI algorithm. These blocks, which are from eSilicon and other IP providers, can be configured using eSilicon’s AI Accelerator. This software will map high-level AI workloads expressed in languages such as TensorFlow to the neuASIC platform and do a quick PPA estimate for the algorithm in the resultant silicon implementation. Having this platform, including the software, allows design exploration of candidate architectures to ensure the design will be within the target specifications. While this architecture is quite flexible, the approach also supports algorithm changes that result in minor chip modifications such as tile changes or modifications to the 2.5D package used to accommodate changes in memory components. More details of the neuASIC platform are available here.

Following are some screenshots of a beta release of AI Accelerator. This will give you a feeling for the tool UI and flow.

Figure 2: AI Accelerator user interface
Figure 3: Graphical output of AI Accelerator
Figure 4: Parametric output of AI Accelerator

eSilicon has made a smart move in providing this software for configuring their neuASIC platform. Increasingly, designers are expecting software interfaces to aid them in configuring IP. Asking someone to code RTL with the correct parameters, or to follow instructions in a manual or user guide ignores the sometimes-complex interactions between the various options. The software approach is easier to use and less error-prone.

The AI Accelerator is part of eSilicon’s online Navigator environment for browsing its IP. Visit eSilicon’s STAR login page to access Navigator, or to sign up for a new account. It’s free. AI Accelerator will be available online when Hot Chips begins. In addition to pbtxt (TensorFlow), the software supports prototxt (Caffe) and json or yaml (Keras), used for machine learning applications such as neural networks.

As eSilicon is a Silver sponsor of Hot Chips, they will be providing a demonstration of the AI Accelerator at a tabletop in the main lobby of the event (there are no booths at Hot Chips). In addition to the demo of AI Accelerator, eSilicon will be discussing the content of a new white paper on Chiplets.