How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier
by Mike Gianfagna on 03-11-2024 at 6:00 am

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

For a long time, package engineering was part of the cleanup crew for chip design. The glory was all around the design of advance monolithic chips on the latest technology node. Once the design was done, the package/test team would take the design over the finish line, adding the required I/O specs, lead frame, load board and test … Read More


Intel Ushers a New Era of Advanced Packaging with Glass Substrates

Intel Ushers a New Era of Advanced Packaging with Glass Substrates
by Mike Gianfagna on 09-18-2023 at 10:00 am

Intel Ushers a New Era of Advanced Packaging with Glass Substrates


Intel recently issued a press announcement that has significant implications for the future of semiconductors.  The release announces Intel’s new glass substrate technology. The headline states: Glass substrates help overcome limitations of organic materials by enabling an order of magnitude improvement in design rulesRead More


Emerging Stronger from the Downturn

Emerging Stronger from the Downturn
by Kalar Rajendiran on 05-16-2023 at 6:00 am

Full Flow from HL Synthesis through to GDSII Accelerates the creation of AI IP

It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor… Read More


proteanTecs Technology Helps GUC Characterize Its GLink™ High-Speed Interface

proteanTecs Technology Helps GUC Characterize Its GLink™ High-Speed Interface
by Kalar Rajendiran on 11-15-2022 at 6:00 am

proteanTecs D2D Monitoring Hardware Block Diagram

An earlier post on SemiWiki discussed how deep data analytics helps accelerate SoC product development. The post presented insights into proteanTecs’ technology and quantified the benefits that can be derived by leveraging the software platform for SoC product development. You can review that earlier blog here. The power … Read More


Webinar: The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging

Webinar: The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging
by Admin on 11-07-2022 at 3:10 pm

November 16, 2022 | 9:00 AM PT | 12:00 PM ET | 6:00 PM CET
(A recording will be sent after the live event to all registrants)

The era of chiplets and heterogeneous integration is here. High-end performance packaging will be a $7.87 billion market by 2027, with a 19% CAGR.1

As the semiconductor industry adopts chiplets and heterogeneous… Read More


Upcoming Webinar: 3DIC Design from Concept to Silicon

Upcoming Webinar: 3DIC Design from Concept to Silicon
by Kalar Rajendiran on 01-26-2022 at 10:00 am

Lessons from Existing Multi Die Solutions

Multi-die design is not a new concept. It has been around for a long time and has evolved from 2D level integration on to 2.5D and then to full 3D level implementations. Multiple driving forces have led to this progression.  Whether the forces are driven by market needs, product needs, manufacturing technology availability or EDA… Read More


AI Interposer Power Modeling and HBM Power Noise Prediction Studies

AI Interposer Power Modeling and HBM Power Noise Prediction Studies
by Mike Gianfagna on 02-07-2020 at 6:00 am

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I attended a session on 2.5D silicon interposer analysis at DesignCon 2020. Like many presentations at this show, ecosystem collaboration was a focus. In this session, Jinsong Hu (principal application engineer at Cadence) and Yongsong He (senior staff engineer at Enflame Tech) presented approaches for interposer power modeling… Read More


Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes

Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes
by Mike Gianfagna on 02-04-2020 at 10:00 am

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This year is the 25th anniversary for DesignCon.  The show has changed a lot over the years. Today, it’s a vibrant showcase of all aspects of advanced product design – from ICs to boards to systems. The show floor reflects the diverse ecosystem. If you missed it this year, definitely plan to go next year.

The DesignCon technical program… Read More


eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips

eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips
by Randy Smith on 08-13-2019 at 10:00 am

In early May of this year, eSilicon announced the tape-out of a test chip which included the latest additions to its neuASIC™ IP platform. At the upcoming Hot Chips Symposium to be held at Stanford on August 19 and 20, 2019, eSilicon will be demonstrating the software component of this AI-enabling IP platform. At the event, eSilicon… Read More


High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory

High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory
by Mitch Heins on 02-07-2018 at 10:00 am


High Bandwidth Memory (HBM) systems have been successfully used for some time now in the network switching and high-performance computing (HPC) spaces. Now, adding fuel to the HBM fire, there is another market that shares similar system requirements as HPC and that is Artificial Intelligence (AI), especially AI systems doing… Read More