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August 13, 2019August 13, 2019

eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips

eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips
by Randy Smith on 08-13-2019 at 10:00 am
Categories: eSilicon, Semiconductor Services

In early May of this year, eSilicon announced the tape-out of a test chip which included the latest additions to its neuASIC™ IP platform. At the upcoming Hot Chips Symposium to be held at Stanford on August 19 and 20, 2019, eSilicon will be demonstrating the software component of this AI-enabling IP platform. At the event, eSilicon… Read More

July 22, 2019July 19, 2019

eSilicon’s Latest SerDes Solution is Here – And It Took A Village

eSilicon’s Latest SerDes Solution is Here – And It Took A Village
by Randy Smith on 07-22-2019 at 10:00 am
Categories: eSilicon, Semiconductor Services

I recently watched a webinar given by eSilicon about its project to enhance its licensable solution for 56 and 112 Gigabit per second PAM4 & NRZ DSP-based SerDes family in 7nm. I am sure it was complicated enough to coordinate a webinar with a host, a moderator, and three different technical presenters – however when we are talking… Read More

June 1, 2019July 12, 2019

In Their Own Words: eSilicon Corporation

In Their Own Words: eSilicon Corporation
by Daniel Nenni on 06-01-2019 at 8:00 am
Categories: eSilicon, Semiconductor Services

eSilicon was one of the first companies to focus on making the benefits of the fabless semiconductor movement available to a broader range of customers and markets. The company is credited with the creation of the fabless ASIC model. In this section, eSilicon shares some of its history and provides its view of the ever-changing … Read More

May 24, 2019May 24, 2019

400G Ethernet test chip tapes-out at 7nm from eSilicon

400G Ethernet test chip tapes-out at 7nm from eSilicon
by Tom Simon on 05-24-2019 at 10:00 am
Categories: eSilicon, FinFET, TSMC

Since the beginning of May eSilicon has announced the tape-out of three TSMC 7nm test chips. The first of these, a 7nm 400G Ethernet Gearbox/Retimer design, caught my eye and I followed up with Hugh Durdan, their vice president of strategy and products, to learn more about it. Rather than just respin their 56G SerDes, they decided… Read More

May 8, 2019

eSilicon ASICs all in the Google Cloud

eSilicon ASICs all in the Google Cloud
by Daniel Nenni on 05-08-2019 at 12:00 pm
Categories: eSilicon, Semiconductor Services
4 Comments

Having just completed a cloud evaluation for SemiWiki I can tell you why eSilicon chose Google. Simply put, they are working harder to get cloud business. Google ($4B) is the number five cloud provider behind Microsoft ($21.2B), Amazon ($20.4B), IBM ($10.3B) and Oracle ($6.08B). There is a lot of money in the cloud and a lot more … Read More

March 11, 2019May 6, 2019

eSilicon Bucking the Trend at OFC with 7nm SerDes

eSilicon Bucking the Trend at OFC with 7nm SerDes
by Daniel Nenni on 03-11-2019 at 8:00 am
Categories: eSilicon, Events, IP

A recent press release from eSilicon caught my eye. The company has been touting their 7nm SerDes quite a bit lately – reach, power, flexibility, things like that. While those capabilities are important, any high-performance chip needs to work in the context of the system, which usually contains technology from multiple sources.… Read More

February 26, 2019

eSilicon Expands Expertise in 7nm

eSilicon Expands Expertise in 7nm
by Tom Simon on 02-26-2019 at 12:00 pm
Categories: eSilicon, FinFET, RISC-V, Semiconductor Services

At SemiWiki we usually don’t write about the press releases we are sent. However, a recent press release by eSilicon caught my eye and prompted me to call Mike Gianfagna, eSilicon Vice President of Marketing. The press release is not just about one thing, rather it focuses on a number of interesting things that together show their… Read More

February 4, 2019

Getting to 56G Takes The Right Stuff

Getting to 56G Takes The Right Stuff
by Tom Simon on 02-04-2019 at 12:00 pm
Categories: EDA, eSilicon, Semiconductor Services

During the 1940s when aerospace engineers were attempting to break the sound barrier for the first time, they were confronting a slew of new technical issues that had never been dealt with before, and in some cases never seen before. In subsonic flight airflow was predictable and well understood. In crossing the sound barrier, … Read More

December 11, 2018

56G and 112G SerDes Where the rubber meets the road

56G and 112G SerDes Where the rubber meets the road
by Tom Simon on 12-11-2018 at 12:00 pm
Categories: eSilicon, IP, Semiconductor Services

No matter how high the processing capability of a chip, its overall performance is limited by IO speed. This is very similar to a car with low performance tires, a powerful engine will not be able to transfer its energy to the ground effectively. There is quite literally a race going on between core processing and IO speeds for transferring… Read More

November 2, 2018

Playing the Long Game with 56G SerDes

Playing the Long Game with 56G SerDes
by Daniel Nenni on 11-02-2018 at 12:00 pm
Categories: 5G, eSilicon, IP

IP has always been a hot topic on SemiWiki with quite a bit of our readers doing the “make versus buy” analysis. SerDes is one of the more difficult “makes” so it is mostly a “buy” analysis made by networking class ASIC architects and a handful of other applications that demand high performance and throughput. Based on the recent traffic… Read More

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eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips

eSilicon’s Latest SerDes Solution is Here – And It Took A Village

In Their Own Words: eSilicon Corporation

400G Ethernet test chip tapes-out at 7nm from eSilicon

eSilicon ASICs all in the Google Cloud

eSilicon Bucking the Trend at OFC with 7nm SerDes

eSilicon Expands Expertise in 7nm

Getting to 56G Takes The Right Stuff

56G and 112G SerDes Where the rubber meets the road

Playing the Long Game with 56G SerDes

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Recent eSilicon Press

AI Hardware Summit 2019: Booth-to-Booth eSilicon 58G DSP-Based SerDes Demonstration Over a Five-Meter Samtec Copper Cable

eSilicon to debut AI Accelerator software and a new chiplet model at Hot Chips 2019

eSilicon, Samtec and Wild River Technology Offer High-Performance Communications Webinar

eSilicon to Participate in Panel Discussion on Chiplet Design Experience at a Workshop Presented by the Open Compute Project (OCP)

Google and eSilicon at DAC 2019: Doing EDA in the Cloud? Yes, It’s Possible!

eSilicon Technical Advisory Board Members Win Facebook Research Award

eSilicon Announces Production Qualification of 5G Infrastructure ASIC

ESD Alliance CEO Outlook 2019: eSilicon CEO Jack Harding to Participate

eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E/Low Latency) Test Chip

eSilicon Tapes Out 7nm neuASIC IP Platform Test Chip