eSilicon ASICs all in the Google Cloud

eSilicon ASICs all in the Google Cloud
by Daniel Nenni on 05-08-2019 at 12:00 pm

Image RemovedHaving just completed a cloud evaluation for SemiWiki I can tell you why eSilicon chose Google. Simply put, they are working harder to get cloud business. Google ($4B) is the number five cloud provider behind Microsoft ($21.2B), Amazon ($20.4B), IBM ($10.3B) and Oracle ($6.08B). There is a lot of money in the cloud… Read More


Retro-uC: on a road to low-cost, (ridiculously) low-volume ASICs ?

Retro-uC: on a road to low-cost, (ridiculously) low-volume ASICs ?
by Staf_Verhaegen on 09-25-2018 at 7:00 am

Image RemovedI’m a long time reader of SemiWiki; almost from the start. I’ve sometimes been a passionate commenter but as some of you may have noticed my activity lately on the forum was lower. One of the reasons is a project I am working on and I feel honoured I was invited to present the background here on SemiWiki.

I am… Read More


Semiconductor IP Reality Check

Semiconductor IP Reality Check
by Daniel Nenni on 09-19-2018 at 12:00 pm

Image RemovedA robust, proven library of IP is a critical enabler for the entire semiconductor ecosystem. Without it, ASIC design is pretty much impossible, given time-to-market pressures. Said another way, designing IP for your next chip simply doesn’t fit the schedule – most teams have barely enough time to integrate and validate… Read More


Open-Silicon SerDes TCoE Enables Successful Delivery of ASICs for Next-generation, High-Speed Systems

Open-Silicon SerDes TCoE Enables Successful Delivery of ASICs for Next-generation, High-Speed Systems
by Mitch Heins on 06-26-2017 at 12:00 pm

Image RemovedWith 5G cellular networks just around the corner, there is an ever-increasing number of companies working to bring faster communications chips to the market. Data centers are now deploying 100G to handle the increased bandwidth requirements, typically in the form of four 28Gbps channels and that means ASIC designers… Read More


eSilicon Revolutionizes Semiconductor IP Selection and Purchasing!

eSilicon Revolutionizes Semiconductor IP Selection and Purchasing!
by Daniel Nenni on 09-21-2016 at 10:00 am

Image RemovedDesign starts are the lifeblood of the semiconductor industry which is why we have been following the eSilicon STAR Platform since its introduction with great anticipation. The STAR platform was first launched about three years ago. Today, there are over 1,300 registered STAR users in 52 countries around the world.… Read More


Blue Pearl adds RTL project transparency at #53DAC

Blue Pearl adds RTL project transparency at #53DAC
by Don Dingee on 06-03-2016 at 4:00 pm

You’re an RTL pro. You know what’s inside your code, and how many bugs you’ve tracked down and exterminated along the development path, and how much work remains. So, why did the meeting notice that just popped up asking for a monthly management project review presentation ruin your day?… Read More


Aldec extends FPGA and ASIC flows at DAC

Aldec extends FPGA and ASIC flows at DAC
by Don Dingee on 05-20-2016 at 4:00 pm

Aldec tools and services have long been associated with FPGA designs. As FPGAs have evolved toward more RTL-based designs, the similarities between a modern FPGA verification flow and an ASIC verification flow often leave them looking virtually the same. … Read More


Enterprise design management engineered for SoCs

Enterprise design management engineered for SoCs
by Don Dingee on 04-22-2016 at 4:00 pm

In my initial look at ClioSoft’s design management system created from the ground up for the semiconductor industry, I made the opening case for managing and reusing IP across an ASIC design organization. Let’s for a moment say we agree on the need for an enterprise software package to do design management… Read More


Cross-viewing improves ASIC & FPGA debug efficiency

Cross-viewing improves ASIC & FPGA debug efficiency
by Don Dingee on 04-20-2016 at 4:00 pm

We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is easier… Read More


More FPGA-based prototype myths quashed

More FPGA-based prototype myths quashed
by Don Dingee on 08-03-2015 at 12:00 pm

Speaking of having the right tools, FPGA-based prototyping has become as much if not more about the synthesis software than it is about the FPGA hardware. This is a follow-up to my post earlier this month on FPGA-based prototyping, but with a different perspective from another vendor. Instead of thinking about what else can be done… Read More